PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 30

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

3
3.1
Figure 4
• S/T-interface transceiver supporting the modes TE, LT-T, LT-S, NT and Intelligent NT
• Different host interface modes:
• Optional indirect register address mode reduces number of registers to be accessed
• One D-channel HDLC-controller with 64 byte FlFOs per direction with programmable
• Support of firmware download via one B-channel HDLC-controller and FlFOs with
• IOM-2 interface for terminal (TE mode), linecard (LT-T or LT-S) or NT applications
• IOM handler with controller data access registers (CDA) allows flexible access to IOM
• Synchronous transfer interrupts (STI) allow controlled access to IOM timeslots
• Flexible timeslot assignment of HDLC controllers on IOM for IDSL support
• MONITOR channel handler on IOM-2 for master mode, slave mode or data exchange
• C/I-channel handler and TIC bus access controller
• D-channel access mechanism in all modes
• D-channel priority handler on IOM-2 for intelligent NT applications
• Capability to control the start of the multiframe for synchronization from external
• Auxiliary interface with interrupt and general purpose I/O lines and 2 LED drivers
• LED connected to pin ACL indicates S-interface activation status automatically or can
• Level detect circuit on the S interface reduces power consumption in power down
• Two timers for periodic or single interrupts (periods between 1 ms and 14.336 s)
• Clock and timing generation
• Digital PLL to synchronize the transceiver to the S/T interface
• Buffered 7.68 MHz oscillator clock output allows connection of further devices and
• Reset generation (watchdog timer)
Data Sheet
- Parallel microcontroller interface
- Serial Control Interface (SCI)
to two locations
FIFO block size (threshold) of 4, 8, 16 or 32 byte for receive direction and 16 or 32
byte for transmit direction
reduced functionality
timeslots for reading/writing, looping and shifting data
signals (M-bit input pin in LT-S/NT mode, M-bit output pin in TE, LT-T mode)
be controlled by the host
mode
saves another crystal on the system board
(Siemens/Intel multiplexed, Siemens/Intel non multiplexed, Motorola modes)
shows the architecture of the ISAC-SX containing the following functions:
Description of Functional Blocks
General Functions and Device Architecture
30
Description of Functional Blocks
PEB 3086
2003-01-30
ISAC-SX