PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 209

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MOCR
4.4.18
Value after reset: 00
MRE ... MONITOR Receive Interrupt Enable
0: MONITOR interrupt status MDR generation is masked
1: MONITOR interrupt status MDR generation is enabled
MRC ... MR Bit Control
Determines the value of the MR bit:
0: MR is always ’1’. In addition, the MDR interrupt is blocked, except for the first byte of
1: MR is internally controlled by the ISAC-SX according to MONITOR channel protocol.
MIE ... MONITOR Interrupt Enable
MONITOR interrupt status MER, MDA, MAB generation is enabled (1) or masked (0).
MXC ... MX Bit Control
Determines the value of the MX bit:
0: The MX bit is always ’1’.
1: The MX bit is internally controlled by the ISAC-SX according to MONITOR channel
protocol.
Data Sheet
a packet (if MRE = 1).
In addition, the MDR interrupt is enabled for all received bytes according to the
MONITOR channel protocol (if MRE = 1).
7
MOCR - MONITOR Control Register
MRE
MRC
H
MIE
MXC
209
0
0
Detailed Register Description
0
0
0
RD/WR (5E)
PEB 3086
2003-01-30
ISAC-SX