PEB3086FV14XT Lantiq, PEB3086FV14XT Datasheet - Page 62

• Manufacturer Part Number: PEB3086FV14XT
• Manufacturer: Lantiq

Specifications of PEB3086FV14XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Supplier Unconfirmed

ISAC-SX
PEB 3086
Description of Functional Blocks
Protection Circuit for Receiver
Figure 30
illustrates the external circuitry used in combination with a symmetrical
receiver. Protection of symmetrical receivers is rather simple.
1:1
S Bus
Note: up to 10 pF capacitors are optional for noise reduction
Figure 30
External Circuitry for Symmetrical Receivers
Between each receive line and the transformer a 10 k W resistor is used. This value is
split into two resistors: one between transformer and protection diodes for current limiting
during the 96 kHz test, and the second one between input pin and protection diodes to
limit the maximum input current of the chip.
With symmetrical receivers no difficulties regarding LCL measurements are observed;
compensation networks thus are obsolete.
In order to comply to the physical requirements of ITU-T recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the ISAC-SX may need additional circuitry.
3.3.7.2
S-Transceiver Synchronization
Synchronization problems can occur on a S-Bus that is not terminated properly.
Therefore, it is recommended to change the resistor values in the receive path. The sum
of both resistors is increased from 10 k W (1.8 + 8.2) to e.g. 34 k W (6.8 + 27) for either
receiver line. This change is possible but not necessary for a S-Bus that is terminated
properly.
Data Sheet
62
2003-01-30