PSB21383H-V13 Infineon Technologies, PSB21383H-V13 Datasheet - Page 109

• Manufacturer Part Number: PSB21383H-V13
• Manufacturer: Infineon Technologies

Specifications of PSB21383H-V13

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

The transfer protocol between HDLC FIFO and microcontroller is block orientated with
the microcontroller as master. The control of the data transfer between the CPU and the
HDLC controller is handled via interrupts (HDLC controller
(Host
There are three different interrupt indications in the ISTAH register concerned with the
reception of data:
– RPF (Receive Pool Full) interrupt, indicating that a data block of the selected length
– RME (Receive Message End) interrupt, indicating that the reception of one message
– RFO (Receive Frame Overflow) interrupt, indicating that a complete frame could not
There are two control commands (bits of CMDR) that are used with the reception of data:
– RMC (Receive Message Complete) command, telling the HDLC controller that a data
– RRES (Receiver Reset) command, resetting the HDLC receiver and clearing the
Data Sheet
(EXMR.RFBS) can be read from RFIFO. The message which is currently received
exceeds the block size so further blocks will be received to complete the message.
is completed, i.e. either
• a short message is received
• the last part of a long message is received
be stored in RFIFO and is therefore lost as the RFIFO is occupied. This occurs if the
host fails to respond quickly enough to RPF/RME interrupts since previous data was
not read by the host.
block has been read from the RFIFO and the corresponding FIFO space can be
released for new receive data.
receive FIFO of any data (e.g. used before start of reception). It has to be used after
having changed the mode.
(message length
(message length
and is stored in the RFIFO.
HDLC controller).
the defined block size (EXMR.RFBS) or
the defined block size (EXMR.RFBS))
99
Host) and commands
HDLC Controller
PSB 21381/2
PSB 21383/4
2001-03-12