PSB21383H-V13 Infineon Technologies, PSB21383H-V13 Datasheet - Page 214

• Manufacturer Part Number: PSB21383H-V13
• Manufacturer: Infineon Technologies

Specifications of PSB21383H-V13

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
7.2.10
Value after reset: 01
ISTA
For all interrupts in the ISTA register following logical states are applied:
0: Interrupt is not activated
1: Interrupt is activated
ST
When programmed (STI register), this interrupt is generated to enable the
microcontroller to lock on to the IOM timing, for synchronous transfers.
CIC
A change in C/I channel 0 or C/I channel 1 has been recognized. The actual value can
be read from CIR0 or CIR1.
TIN
The internal timer and repeat counter has expired (see TIMR register).
WOV
Used only if terminal specific functions are enabled (MODE.TSF=1).
Signals the expiration of the watchdog timer, which means that the microcontroller has
failed to set the watchdog timer control bits WTC1 and WTC2 (ADF1 register) in the
correct manner. A reset pulse has been generated by the SCOUT.
TRAN
An interrupt originated in the transceiver interrupt status register (ISTATR) has been
recognized.
MOS
A change in the MONITOR Status Register (MOSR) has occurred.
HDLC
An interrupt originated in the HDLC interrupt sources has been recognized.
Note: A read of the ISTA register clears only the TIN and WOV interrupts. The other
interrupts are cleared by reading the corresponding status register
ISTA - Interrupt Status Register
7
0
... C/I Channel Change
... Timer Interrupt
... Watchdog Timer Overflow
... Transceiver Interrupt
... MONITOR Status
... HDLC Interrupt
... Synchronous Transfer
H
ST
CIC
TIN
204
WOV TRAN MOS HDLC
Detailed Register Description
0
PSB 21381/2
PSB 21383/4
2001-03-12
RD (3C
H
)