PSB21383H-V13 Infineon Technologies, PSB21383H-V13 Datasheet - Page 168

• Manufacturer Part Number: PSB21383H-V13
• Manufacturer: Infineon Technologies

Specifications of PSB21383H-V13

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
4.8.2
The codec registers (60
chapter 2.1 and 4.8.2.1).
4.8.2.1
For the direct access to individual CRAM coefficients via microcontroller a back-up
procedure is provided. This ensures that the codec DSP always works with a consistent
and valid coefficient block during the changing of CRAM parameters. The following
section describes this back-up procedure.
Note: For the ARCOFI compatible programming sequence (see chapter 2.1.1.1) such a
The control of the back-up procedure is done with the CRAM Control Register (CCR) and
the CRAM Status Register (CSR).The Control and Status bits in these registers are
explained in the following section:
CRAM Block Address (CBADR)
The CRAM range (80
CBADR = ’0
coefficents corresponds to the COP_x sequences of the ARCOFI (see table 25 and
chapter 4.8.1.1).
DSP CRAM Access (DCA)
By setting this bit it is possible to select whether the codec DSP has access to the CRAM
blocks in the normal CRAM range (’0’) or to a temporary 8-byte CRAM block (’1’).
Start Back-up Procedure (SBP)
Setting this bit starts the transfer of a CRAM block (CBADR) to the temporary 8-byte
CRAM block.
Busy Back-up Procedure (BSYB)
This status bit indicates if a transfer of a CRAM block (CBADR) to the temporary 8-byte
CRAM block is running (’1’) or not (’0’). If the transfer is running no CRAM access via
microcontroller interface is allowed.
Figure 87 shows the access structure of CRAM and temporary CRAM. Figure 88 gives
a signal flow of the back-up procedure of a CRAM block x (x = 0...F).
back-up procedure for the CRAM blocks is not necessary because it is done
automatically.
Direct Programming of the Codec
CRAM Back-Up Procedure
H
’ to ’F
H
’. Each coefficent block has 8 bytes. The mapping of the CRAM
H
to FF
H
-6F
H
H
) is subdivided in 16 CRAM blocks with the block address
) and the CRAM (80
158
H
-FF
H
) are directly accessible (see
PSB 21381/2
PSB 21383/4
2001-03-12
Codec