MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 110

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

13–4
13.1.3.2
13.2
NT Terminal Mode
In NT Terminal mode, another IDL2 channel data port is opened on the device. This port has four
pins associated with it. They are DREQUEST, DGRANT, CLASS, and T_IN.
This port has the capability of competing for access to the D channel with the TEs connected to the
passive bus. To do this, the DREQUEST, DGRANT, and CLASS functions normally associated with
the TE are enabled. This allows an external controlling device to request access to the D channel,
and if the D channel is idle, be given access. The NT device monitors the received S/T loop D bits
to determine whether the channel is busy or not (a TE device would monitor the E bits).
Once the controlling device has been given access to the D channel, the MC145574 indicates this
by setting DGRANT high and enabling the D slot on the T_IN pin.
The NT device ANDs the received D bits from the S/T loop with D channel data received from the
T_IN pin, and transmits this as the E bit on the S/T loop. The AND’d data is then passed to the D out
for output.
DGRANT is high when the S/T is not activated.
Contention is monitored by comparing the transmitted E bit to the D channel data from the T_IN pin.
If they are not equal then contention from a device on the S/T loop is assumed, and the D channel
access halted. An interrupt IRQ7, NR3(0), is generated to indicate contention has occurred.
The T_IN pin also accepts data on the B1 and B2 slots. This data is AND’d with the received B1 and
B2 data from the S/T–interface and then output on the D out pin. There is no provision on the device
to detect data collision on the B channels. (The B channels are enabled by default.)
The T_IN IDL2 port is synchronized to the normal IDL2 port by FSC, and the DCL clock is used to
sample the T_IN pin. NT Terminal mode operates in all the IDL2 modes, including TSA and dual frame
sync modes.
When the D out pin is configured as an open drain output, a pullup resistor (between 1 k and 10 k)
is needed.
The T_IN port has the same format as the IDL2 or GCI that is being used.
Data can be input to the T_IN pin when the MC145574 is either activated or deactivated. NT Terminal
mode operates when the MC145574 is either activated or deactivated.
TE CONFIGURATIONS
To select TE mode, Pin 4 (TE/NT) must be held high, or alternatively, by writing to the SCP control
bit OR8(4). This bit is internally OR’d with the TE/NT pin. In TE mode, the device operates in two
different configurations, these configurations being TE slave (TES) and TE master (TEM).
The selection of slave or master is accomplished via Pin 5. When held low, slave mode is selected;
and when held high, master mode is selected.
Each mode is discussed separately in the following sections; however, certain shared pins have differ-
ent functions in TES and TEM mode. (See Table 13–2.)
There is no fixed/adaptive timing selection to be made in TE mode. In TE mode, the MC145574 always
uses adaptive timing.
TQFP Pin 3
TQFP Pin 5
TQFP Pin 6
TQFP Pin 7
Table 13–2. Pin Operations for Master and Slave
Pin
MC145574
SOIC Pin 6
SOIC Pin 8
SOIC Pin 9
SOIC Pin 10
Modes
High–Z
DGRANT
DREQUEST
CLASS
TEM
TFSC/TCLK
High–Z
Tie V SS
Tie V SS
TES
MOTOROLA