MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 73

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

MOTOROLA
8.6
INFO 1, INFO 3, or INFO X state. Alternatively, in the TE mode, this corresponds to a change in the
receiving INFO 0, INFO 2, INFO 4, or INFO X state. Thus, when a change occurs in one of these
states, the MC145574 internally sets this bit. An external interrupt will occur if “Enable IRQ3” (NR4(3))
is set. IRQ3 can be cleared by writing a 0 to NR3(3). This bit is reset by a software or a hardware
reset.
Note that the transmission states for the NT (INFO 0, INFO 2, and INFO 4) and for the TE (INFO 0,
INFO 1, and INFO 3) are as defined in Section 3. INFO X is defined as any transmission state other
than those states. An example of such a state would be when the MC145574 is programmed to transmit
a 96 kHz test tone (BR11(0) = 1). Note that NR3(3) is a read/write bit.
An INFO X state interrupt is generated only when receive INFO X state has persisted for > 8 ms.
This avoids spurious interrupts during transient INFO X changes seen during activation but allows
indication of prolonged INFO X conditions.
NR3(2) — Multiframe Reception IRQ2
This bit is for multiframe detection indication. Multiframing is initiated by the NT by setting BR7(5).
A multiframe is 20 basic frames or 5 ms in duration. If this interrupt is enabled by setting NR4(2) and
if multiframing is in progress, then an interrupt will be generated on multiframe boundaries; i.e., every
5 ms. Alternatively, an NT–configured MC145574 can be programmed to generate an interrupt only
in the event of a new Q channel nibble having been received. Similarly, a TE–configured MC145574
can be programmed to generate an interrupt only in the event of a new SC1 subchannel having been
received. Refer to Section 12 for a detailed description of these features.
A mutiframing interrupt is cleared by reading BR3. Reading BR3 will clear the interrupt in both the
NT and TE modes of operation, regardless of whether the MC145574 is configured to generate an
interrupt in the event of a new nibble or every multiframe. Note that NR3(2) is a read only bit.
NR3(1)
NT: IRQ6 FECV Detection — The IRQ6 status bit is set when the NT has detected a far–end code
violation. See Section 15.6 for more details.
TE: D Channel Collision IRQ1 — NR3(1) is an interrupt bit used to indicate to external devices
that a collision has occurred on the D channel. A D channel collision is considered to have occurred
when the TE is transmitting on the D channel (both DREQUEST and DGRANT being high), and the
received E echo bit from the NT does not match the previously modulated D bit. The interrupt condition
is cleared by writing a 0 to NR3(1). This bit is maskable by means of NR4(1). Note that NR3(1) is
a read/write bit.
NR3(0) — NT: D Channel Collision IRQ7 NT Terminal Mode
NR3(0) is an interrupt bit used to indicate to external devices that a collision has occurred on the
D channel. A D channel collision is considered to have occurred when the NT is transmitting on the
IDL2 Tx D channel via the T_IN input pin (both DREQUEST and DGRANT being high), and the trans-
mitted E echo bit to the TE does not match the previously input T_IN bit. The interrupt condition is
cleared by writing a 0 to NR3(0). This bit is maskable by means of NR4(0). Note that NR3(0) is a
read/write bit.
NR4
This register is a read/write register and can be reset by application of either a hardware or software
reset. A per–bit description of nibble register 4 (NR4) follows.
NR4
TE: Not Applicable
Enable IRQ3
b3
rw
MC145574
Enable IRQ2
b2
rw
NT: Enable IRQ6
TE: Enable IRQ1
b1
rw
TE: Not Applicable
NT: Enable IRQ7
b0
8–5
rw