MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 34

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

4–8
4.3.6.6
Independent timeslot assignment is available for the B1, B2, and D channels in both the transmit and
receive directions. B1, B2, and D timeslots may be enabled separately. When a timeslot is enabled,
the IDL2 automatically enters timeslot mode. If any one channel’s timeslot is not enabled, data trans-
mitted by the framer for that channel will be filled with all ones, and the channel will not be present
on D out .
With a DCL rate of 4096 kHz, it is possible to allocate 1 of 256 possible timeslots to each data channel.
It is important that the software selects a timeslot consistent with the DCL rate. When a clock rate
of 2048 kHz is being used, only 128 timeslots are available. If a timeslot out with the available range
is chosen, then no data transfer occurs for that timeslot.
The default values assigned to the B1, B2, and D channels are 00H, 04H, and 08H. These values
provide an IDL2 8–bit output format as default.
The IDL2 10–bit mode is not available when the timeslot assigner has been enabled.
Short and Long Framing
In master timing mode, the default state is to supply a one–clock–wide FSC/FSR/FST frame sync.
However, an option is provided to change this to long frame. The length of the long frame pulse is
always 8–bit clocks, regardless of whether an 8– or 10–bit format is selected. In the slave mode, the
MC145574 will automatically adjust to whichever framing method is supplied. If the frame sync is two
or more clocks wide, the MC145574 assumes a long frame format.
A long frame format cannot be used in timeslot assignment mode.
S–INTERFACE
SUBSCRIBER
Do not program overlapping timeslots even if a timeslot has not been enabled. The transmit
and receive timeslot for a given B1, B2, or D channel can be the same.
LINES
S
S
S
S
NT
NT
NT
NT
SYNC
SYNC
SYNC
SYNC
DATA
DATA
DATA
DATA
CLK
CLK
CLK
CLK
Figure 4–4. Example Architecture of an NT2
MC145574
CLK
TSA CONTROLLER
SYNC AND CLOCK
FSC SOURCE
GENERATOR
SELECTOR
CAUTION
FRAME SYNC
CONTROL
BUS
TFSC
CLK
SYNC
DATA
TFSC
CLK
SYNC
DATA
TFSC
CLK
SYNC
DATA
TFSC
CLK
SYNC
DATA
TO CENTRAL OFFICE(S)
TE
TE
TE
TE
MOTOROLA
T–INTERFACE
TRUNK LINES
T
T
T
T