MC145574APB Freescale Semiconductor, MC145574APB Datasheet - Page 30

• Manufacturer Part Number: MC145574APB
• Description: IC TRANSCEIVER ISDN 32-LQFP
• Manufacturer: Freescale Semiconductor
• Type: Transceiverr

Specifications of MC145574APB

• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Not Compliant

4–4
4.3.6.1
4.3.6.2
4.3.6.3
4.3.6.4
4.3.6.5
4.3.6
Additional Notes
Phase Relationship of the NT Transmit Signal with Respect to FSC/FSR
The MC145574 operating as an NT behaves as an IDL2 slave, FSC/FSR and DCL being inputs to
the device. FSC/FSR is a single positive polarity pulse, one DCL cycle in duration, and is periodic
at an 8 kHz rate. The MC145574 operating as an NT uses FSC/FSR to correctly position its outbound
waveform. Thus, the FSC/FSR input to the NT and the NT’s outbound INFO 2 or INFO 4 are synchro-
nous. The phase relationship of these signals is shown in Figure 4–1 with a “close–up shot” included.
Phase Relationship of the TE Transmit Signal with Respect to FSC/FSR, When in
the IDL2 Master Mode
The MC145574 operating as a TE behaves as an IDL2 master; FSC/FSR and DCL are outputs from
the device. The TE derives its timing from the inbound INFO 2 or INFO 4 from the NT. There is a
two–baud turnaround in the TE in accordance with CCITT I.430, ETSI ETS 300012, and ANSI T1.605
specifications; i.e., the time between the TE’s received “F bit” and its transmitted “F bit” is equivalent
to two bauds. This is indicated in Figure 4–2. The TE outputs FSC/FSR, DCL, and D out when it has
achieved frame synchronization. The phase relationship of the TE’s transmitted INFO 3 and FSC/FSR
is as shown in Figure 4–3 with a “close–up shot” included.
Operation of Multiple MC145574s in TE Slave Mode
When the MC145574 is configured for TE slave mode in NT2 applications, the T_IN/TFSC/TCLK/FIX
pin defaults to the TFSC function. As TFSC, this pin outputs an 8 kHz frame sync that is synchronized
to recovered timing from the network.
In TE slave mode, the T_IN/TFSC/TCLK/FIX pin function can be changed to TCLK, which outputs
a network synchronized high frequency clock. This is done by setting OR7(5) to a 1. The clock frequen-
cy of TCLK is selected in the same manner as programming the DCL clock in IDL2 master mode.
Elastic buffers are included in TE slave mode to allow the MC145574 to operate with any phase relation-
ship between the IDL2 frame sync and the network. This buffer also allows the frame sync to wander
with respect to the network, up to 60 s peak–to–peak. This exceeds the requirements of Q.502, which
states that wander up to 18 s peak–to–peak may arise over a 24–hour period.
An example architecture of an NT2 is shown in Figure 4–4. The TFSC or TCLK signal supplied by
the TE is used to synchronize the entire NT2 to the network. The TFSC/TCLK pins can be wire OR’d
together and connected to V DD via a pull–up resistor. Each TE looks at the TFSC/TCLK pin during
its programmed B1 channel timeslot. If there is no signal present and the TE is activated, it outputs
a synchronized signal on TFSC/TCLK. It is important for all TEs to have their B and D channels config-
ured using the timeslot assigner, and no two devices can share a timeslot.
Independent Tx/Rx Frame Syncs
Via the SCP, two pins (FST and FSR) are available to handle the transmit and receive frames indepen-
dently on the IDL2 interface. These pins must operate synchronously with the DCL clock. Operation
of FST and FSR is dependent on the master or slave mode. Separate frame syncs are enabled by
setting OR7(4) to a 1.
In the slave mode, FST and FSR may assume any relationship with respect to each other.
In the master mode, both FST and FSR are operational and locked together in time. Long frame format
can not be used with independent Tx/Rx frame syncs.
Timeslot Assignment
The MC145574 contains a timeslot assigner. The timeslot immediately following the FSC/FSR/FST
signal is timeslot zero. Timeslots are available up to the maximum DCL rate of 4096 kHz. The timeslots
are programmed through a group of control registers in the overlay register map. Up to 256 start times
may be defined, corresponding to each 2–bit boundary defined by DCL.
MC145574
MOTOROLA