DS1877T+ Maxim Integrated Products, DS1877T+ Datasheet - Page 22

• Manufacturer Part Number: DS1877T+
• Description: IC CTLR/MON SFP 1-2CH 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1877T+

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 2.5mA
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1877T+000

SFP Controller for Dual Rx Interface
Figure 13. Example I
22
A)
B)
C)
D)
TYPICAL I
*IF ASEL IS 0, THE SLAVE ADDRESS IS A0h FOR THE AUXILIARY MEMORY AND A2h/B2h FOR THE MAIN MEMORY.
IF ASEL = 1, THE SLAVE ADDRESS IS DETERMINED BY TABLE 02h, REGISTER 8Bh FOR THE MAIN MEMORY. THE AUXILIARY MEMORY CONTINUES TO BE ADDRESSED AT A0h, EXCEPT WHEN THE PROGRAMMED
ADDRESS FOR THE MAIN MEMORY IS A0h.
EXAMPLE I
START
To prevent address wrapping from occurring, the
master must send a STOP condition at the end of
the page, then wait for the bus-free or EEPROM write
time to elapse. Then the master can generate a new
START condition and write the slave address byte
(R/W = 0) and the first memory address of the next
memory row before continuing to write data.
Acknowledge Polling: Any time a EEPROM page is
written, the device requires the EEPROM write time
(t
the page to EEPROM. During the EEPROM write time,
the device does not acknowledge its slave address
because it is busy. It is possible to take advantage
of that phenomenon by repeatedly addressing the
device, which allows the next page to be written as
soon as the device is ready to receive the data. The
alternative to acknowledge polling is to wait for maxi-
mum period of t
write again to the device.
SINGLE-BYTE WRITE
-WRITE 00h TO REGISTER BAh
SINGLE-BYTE READ
-READ REGISTER BAh
TWO-BYTE WRITE
-WRITE 01h AND 75h TO
REGISTERS C8h AND C9h
TWO-BYTE READ
-READ C8h AND C9h
WR
2
C WRITE TRANSACTION
2
MSB
) after the STOP condition to write the contents of
C TRANSACTIONS WITH A2h AS THE MAIN MEMORY DEVICE ADDRESS
X
X
X
ADDRESS*
SLAVE
2
X
C Timing
WR
START
START
START
START
0
to elapse before attempting to
0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 1 0 0 0 1 0
1
A2h
A2h
A2h
A2h
WRITE
READ/
LSB
R/W
SLAVE
SLAVE
SLAVE
SLAVE
SLAVE
ACK
ACK
ACK
ACK
ACK
MSB
1 0 1 1 1 0 1 0
1 0 1 1 1 0 1 0
1 1 0 0 1 0 0 0
1 1 0 0 1 0 0 0
b7
BAh
BAh
C8h
C8h
b6
b5
REGISTER ADDRESS
SLAVE
SLAVE
SLAVE
SLAVE
ACK
ACK
ACK
ACK
b4
b3
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1
REPEATED
REPEATED
START
START
b2
00h
01h
b1
EEPROM Write Cycles: When EEPROM writes
occur, the device writes the whole EEPROM memory
page, even if only a single byte on the page was
modified. Writes that do not modify all 8 bytes on the
page are allowed and do not corrupt the remaining
bytes of memory on the same page. Because the
whole page is written, bytes on the page that were
not modified during the transaction are still subject to
a write cycle. This can result in a whole page being
worn out over time by writing a single byte repeatedly.
Writing a page 1 byte at a time wears the EEPROM
out 8x faster than writing the entire page at once. The
device’s EEPROM write cycles are specified in the
Nonvolatile Memory Characteristics table. The speci-
fication shown is at the worst-case temperature. It can
handle approximately 10x that many writes at room
temperature. Writing to SRAM-shadowed EEPROM
memory with SEEB = 1 does not count as a EEPROM
write cycle when evaluating the EEPROM’s estimated
lifetime.
1 0 1 0 0 0 1 1
1 0 1 0 0 0 1 1
LSB
SLAVE
SLAVE
b0
ACK
ACK
A3h
A3h
SLAVE
ACK
0 1 1 1 0 1 0 1
STOP
75h
SLAVE
SLAVE
ACK
ACK
MSB
b7
b6
DATA IN BAh
DATA IN C8h
SLAVE
ACK
DATA
DATA
b5
STOP
b4
DATA
MASTER
MASTER
b3
NACK
ACK
b2
STOP
DATA IN C9h
b1
DATA
LSB
b0
SLAVE
ACK
MASTER
NACK
STOP
STOP