DS1877T+ Maxim Integrated Products, DS1877T+ Datasheet - Page 42

• Manufacturer Part Number: DS1877T+
• Description: IC CTLR/MON SFP 1-2CH 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1877T+

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 2.5mA
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1877T+000

SFP Controller for Dual Rx Interface
Table 01h, Register FBh: ALARM EN
Table 01h, Register FCh: WARN EN
42
FBh
FCh
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
Layout is identical to ALARM
whether this memory exists in Table 01h or 05h.
BITS 5:0
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
Layout is identical to WARN
Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.
LOS HI
BIT 7
BIT 7
BIT 6
TEMP HI
BITS 3:0
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
LOS HI: Enables alarm to create FLTINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS HI alarm.
1 = Enables interrupt from LOS HI alarm.
LOS LO: Enables alarm to create FLTINT (Lower Memory, Register 71h) logic.
0 = Disables interrupt from LOS LO alarm.
1 = Enables interrupt from LOS LO alarm.
RESERVED
LOS LO
TEMP HI [A2h or B2h]:
0 = Disables interrupt from the TEMP HI warning.
1 = Enables interrupt from the TEMP HI warning.
TEMP LO [A2h or B2h]:
0 = Disables interrupt from the TEMP LO warning.
1 = Enables interrupt from the TEMP LO warning.
VCC HI [A2h or B2h]:
0 = Disables interrupt from the VCC HI warning.
1 = Enables interrupt from the VCC HI warning.
VCC LO [A2h or B2h]:
0 = Disables interrupt from the VCC LO warning.
1 = Enables interrupt from the VCC LO warning.
RESERVED
TEMP LO
3
00h
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
PW2 or (PW1 and RWTBL1C)
Different A2h and B2h memory locations
Nonvolatile (SEE)
0
3
in Lower Memory, Register 74h. Enables warnings to create FLTINT (Lower Memory,
RESERVED
0
in Lower Memory, Register 73h. The MASK bit (Table 02h, Register 88h) determines
00h
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
PW2 or (PW1 and RWTBL1C)
Common A2h and B2h memory locations
Nonvolatile (SEE)
VCC HI
RESERVED
VCC LO
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BIT 0
BIT 0