DS1877T+ Maxim Integrated Products, DS1877T+ Datasheet - Page 23

• Manufacturer Part Number: DS1877T+
• Description: IC CTLR/MON SFP 1-2CH 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1877T+

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 2.5mA
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1877T+000

The device features memory tables that are internally
organized into 8-byte rows. The main device located at
A2h is used for overall device configuration and receiver
1 control, calibration, alarms, warnings, and monitoring.
Lower Memory, A2h is addressed from 00h−7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, password entry area (PWE),
and the table-select byte.
Table 01h, A2h primarily contains user EEPROM (with
PW1 level access) as well as alarm and warning enable
bytes.
Table 02h, A2h is a multifunction space that contains
configuration registers, scaling and offset values, pass-
words, and interrupt registers as well as other miscel-
laneous control bytes.
Table 04h, A2h contains a temperature-indexed LUT for
control of the DAC1 voltage. The DAC1 LUT can be pro-
grammed in 2NC increments over the -40NC to +102NC
Reading a Single Byte from a Slave: Unlike the
write operation that uses the memory address byte
to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
slave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, and
generates a STOP condition.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
pointer to a particular value. To do this, the mas-
ter generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated START
condition, writes the slave address byte (R/W = 1),
reads data with ACK or NACK as applicable, and
generates a STOP condition.
Memory Organization
SFP Controller for Dual Rx Interface
range. It also contains an LUT for temperature-controlled
offsets for DAC1.
Table 05h, A2h is empty by default. It can be config-
ured to contain the alarm and warning enable bytes
from Table 01h, Registers F8h−FFh with the MASK bit
enabled (Table 02h, Register 88h). In this case Table
01h is empty.
The main device located at B2h is used for receiver 2
control, calibration, alarms, warnings, and monitoring.
Lower Memory, B2h is addressed from 00h−7Fh and
contains alarm and warning thresholds, flags, masks,
several control registers, PWE, and the table-select byte.
Table 01h, B2h contains alarm and warning enable
bytes.
Table 02h, B2h is a multifunction space that contains
configuration registers, scaling and offset values, pass-
words, interrupt registers as well as other miscellaneous
control bytes. Table 02h, B2h only contains functions
related to receiver 2. All other functions are controlled by
Table 02h, A2h.
Table 04h, B2h contains a temperature-indexed LUT for
control of the DAC2 voltage. The DAC2 LUT can be pro-
grammed in 2NC increments over the -40NC to +102NC
range. It also contains an LUT for temperature-controlled
offsets for DAC2.
Table 05h, B2h is empty by default. It can be config-
ured to contain the alarm and warning-enable bytes
from Table 01h, Registers F8h−FFh with the MASK bit
enabled (Table 02h, Register 88h). In this case Table
01h is empty.
Auxiliary Memory (Device A0h) contains 256 bytes
of EE memory accessible from address 00h−FFh. It is
selected with the device address of A0h.
See the Register Descriptions section for a more com-
plete detail of each byte’s function, as well as for read/
write permissions for each byte.
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