DS1877T+ Maxim Integrated Products, DS1877T+ Datasheet - Page 40

• Manufacturer Part Number: DS1877T+
• Description: IC CTLR/MON SFP 1-2CH 28TQFN
• Manufacturer: Maxim Integrated Products
• Type: SFP+ Controllerr

Specifications of DS1877T+

• Input Type: Logic
• Output Type: Logic
• Interface: I²C
• Current - Supply: 2.5mA
• Mounting Type: Surface Mount
• Package / Case: 28-WFQFN exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 90-1877T+000

Table 01h, Register 80h–F7h: EEPROM
SFP Controller for Dual Rx Interface
Table 01h, Register F8h: ALARM EN
40
80h–F7h
F8h
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
Layout is identical to ALARM
Register 71h) logic. The MASK bit (Table 02h, Register 88h) determines whether this memory exists in Table 01h or 05h.
TEMP HI
BITS 3:0
POWER-ON VALUE
READ ACCESS
WRITE ACCESS
A2h AND B2h MEMORY
MEMORY TYPE
EEPROM for PW1 and/or PW2 level access.
BIT 7
BIT 7
BIT 6
BIT 5
BIT 4
BIT 7
EE
TEMP HI [A2h or B2h]:
0 = Disables interrupt from TEMP HI alarm.
1 = Enables interrupt from TEMP HI alarm.
TEMP LO [A2h or B2h]:
0 = Disables interrupt from TEMP LO alarm.
1 = Enables interrupt from TEMP LO alarm.
VCC HI [A2h or B2h]:
0 = Disables interrupt from VCC HI alarm.
1 = Enables interrupt from VCC HI alarm.
VCC LO [A2h or B2h]:
0 = Disables interrupt from VCC LO alarm.
1 = Enables interrupt from VCC LO alarm.
RESERVED
TEMP LO
EE
3
3
in Lower Memory, Register 70h. Enables alarms to create FLTINT (Lower Memory,
00h
PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C)
PW2 or (PW1 and RWTBL1C)
Common A2h and B2h memory locations
Nonvolatile (SEE)
VCC HI
00h
PW2 or (PW1 and RWTBL1A) or (PW1 and RTBL1A)
PW2 or (PW1 and RWTBL1A)
Common A2h and B2h memory locations
Nonvolatile (EE)
EE
VCC LO
EE
RESERVED
EE
Table 01h Register Descriptions
RESERVED
EE
RESERVED
EE
RESERVED
BIT 0
BIT 0
EE