PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 14

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.2
SECONDARY BUS INTERFACE SIGNALS
Name
P_M66EN
Name
S_AD[31:0]
S_CBE[3:0]
S_PAR
S_FRAME_L
S_IRDY_L
S_TRDY_L
Pin #
102
Pin #
201, 200, 198,
197, 195, 192,
191, 189, 188,
186, 185, 183,
182, 165, 164,
162, 161, 159,
154, 152, 150,
147, 146, 144,
143, 141, 140,
138, 137
194, 180, 167, 149
168
179
177
176
206, 204, 203,
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Pin #
R14
Pin #
A4, D5, C5,
A5, B5, D6,
A6, C6, C7,
A7, B7, C8,
A8, B8, A9,
C9, C12, D12,
A14, B13, A15,
B16, E13, C16,
E14, D16, F13,
E16, F14, F15,
F16, G16
B6, B9, B12,
E15
A13
A10
B10
C10
Type
Type
STS
STS
STS
TS
TS
TS
I
ADVANCE INFORMATION
Description
Primary Interface 66MHz Operation.
This input is used to specify if PI7C8150B is capable of
running at 66MHz. For 66MHz operation on the Primary
bus, this signal should be pulled “HIGH”. For 33MHz
operation on the Primary bus, this signal should be
pulled LOW. In synchronous mode, S_M66EN will be
driven LOW, forcing the secondary bus to run at 33MHz
also. Also, bit [21] offset 04h is determined by CFG66.
If P_M66EN is LOW, S_M66EN will not be driven
LOW (please see S_M66EN pin description).
In asynchronous mode, the logic value of P_M66EN is
used to generate the value of bit[21] offset 04h.
Description
Secondary Address/Data: Multiplexed address and
data bus. Address is indicated by S_FRAME_L
assertion. Write data is stable and valid when
S_IRDY_L is asserted and read data is stable and valid
when S_IRDY_L is asserted. Data is transferred on
rising clock edges when both S_IRDY_L and
S_TRDY_L are asserted. During bus idle, PI7C8150B
drives S_AD to a valid logic level when S_GNT_L is
asserted respectively.
Secondary Command/Byte Enables: Multiplexed
command field and byte enable field. During address
phase, the initiator drives the transaction type on these
pins. The initiator then drives the byte enables during
data phases. During bus idle, PI7C8150B drives
S_CBE[3:0] to a valid logic level when the internal
grant is asserted.
Secondary Parity: Parity is even across S_AD[31:0],
S_CBE[3:0], and S_PAR (i.e. an even number of 1’s).
S_PAR is an input and is valid and stable one cycle after
the address phase (indicated by assertion of
S_FRAME_L) for address parity. For write data phases,
S_PAR is an input and is valid one clock after
S_IRDY_L is asserted. For read data phase, S_PAR is
an output and is valid one clock after S_TRDY_L is
asserted. Signal S_PAR is tri-stated one cycle after the
S_AD lines are tri-stated. During bus idle, PI7C8150B
drives S_PAR to a valid logic level when the internal
grant is asserted.
Secondary FRAME (Active LOW): Driven by the
initiator of a transaction to indicate the beginning and
duration of an access. The de-assertion of S_FRAME_L
indicates the final data phase requested by the initiator.
Before being tri-stated, it is driven to a de-asserted state
for one cycle.
Secondary IRDY (Active LOW): Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the secondary side.
Once asserted in a data phase, it is not de-asserted until
the end of the data phase. Before tri-stated, it is driven
to a de-asserted state for one cycle.
Secondary TRDY (Active LOW): Driven by the target
of a transaction to indicate its ability to complete current
data phase on the secondary side. Once asserted in a
data phase, it is not de-asserted until the end of the data
phase. Before tri-stated, it is driven to a de-asserted state
for one cycle.
April 2009 – Revision 1.08
PI7C8150B