PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 37

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.8.3.1
3.8.3.2
Table 3-7. Delayed Write Target Termination Response
Table 3-8. Response to Posted Write Target Termination
PI7C8150B handles these terminations in different ways, depending on the type of
transaction being performed.
When PI7C8150B initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 3-7 shows the response
to each type of target termination that occurs during a delayed write transaction.
PI7C8150B repeats a delayed write transaction until one of the following conditions is met:
PI7C8150B makes 2
target retry.
After the PI7C8150B makes 2
on the target bus, PI7C8150B asserts P_SERR_L if the SERR_L enable bit (bit 8 of
command register for the secondary bus) is set and the delayed-write-non-delivery bit is
not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register
(offset 64h). PI7C8150B will report system error. See Section 6.4 for a description of
system error conditions.
When PI7C8150B initiates a posted write transaction, the target termination cannot be
passed back to the initiator. Table 3-8 shows the response to each type of target
termination that occurs during a posted write transaction.
DELAYED WRITE TARGET TERMINATION RESPONSE
POSTED WRITE TARGET TERMINATION RESPONSE
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
Target Termination
Normal
Target Retry
Target disconnect
Target abort
PI7C8150B completes at least one data transfer.
PI7C8150B receives a master abort.
PI7C8150B receives a target abort.
24
(default) or 2
Response
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
Repsonse
No additional action.
Repeating write transaction to target.
24
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(default) attempts of the same delayed write trans-action
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
32
(maximum) write attempts resulting in a response of
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B