PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 87

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.31
14.1.32
14.1.33
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h
SECONDARY BUS ARBITER PREEMPTION CONTROL
REGISTER – OFFSET 4Ch
Bit
0
1
15:2
Bit
16
31:17
Bit
31:28
Function
Memory Read
Flow Through
Enable
Park
Reserved
Function
Upstream (S to
P) Memory Base
and Limit Enable
Reserved
Function
Secondary bus
arbiter
preemption
contorl
Type
R/W
R/W
R/O
Type
R/W
R/O
Type
R/W
Page 87 of 109
Description
Controls ability to do memory read flow through
0: Disable flow through during a memory read transaction
1: Enable flow through during a memory read transaction
Reset to 0
Controls bus arbiter’s park function
0: Park to last master
1: Park to bridge
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Description
0: Upstream memory is the entire range except the down stream
memory channel
1: Upstream memory is confined to upstream Memory Base and
Limit (See offset 50
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Description
Controls the number of clock cycles after frame is asserted before
preemption is enabled.
1xxx: Preemption off
0000: Preemption enabled after 0 clock cycles
0001: Preemption enabled after 1 clock cycle
0010: Preemption enabled after 2 clock cycles
0011: Preemption enabled after 4 clock cycles
0100: Preemption enabled after 8 clock cycles
0101: Preemption enabled after 16 clock cycles
0110: Preemption enabled after 32 clock cycles
0111: Preemption enabled after 64 clock cycles
Reset to 0000
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
th
and 54
th
for upstream memory range)
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B