PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 38

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.8.3.3
Table 3-9. Response to Delayed Read Target Termination
Note that when a target retry or target disconnect is returned and posted write data
associated with that transaction remains in the write buffers, PI7C8150B initiates another
write transaction to attempt to deliver the rest of the write data. If there is a target retry, the
exact same address will be driven as for the initial write trans-action attempt. If a target
disconnect is received, the address that is driven on a subsequent write transaction attempt
will be updated to reflect the address of the current DWORD. If the initial write transaction
is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the
target is performed before a target disconnect is received, PI7C8150B will use the memory
write command to deliver the rest of the write data. It is because an incomplete cache line
will be transferred in the subsequent write transaction attempt.
After the PI7C8150B makes 2
posted write data associated with that transaction, PI7C8150B asserts P_SERR_L if the
primary SERR_L enable bit is set (bit 8 of command register for secondary bus) and
posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of
P_SERR_L event disable register (offset 64h). PI7C8150B will report system error. See
Section 6.4 for a discussion of system error conditions.
DELAYED READ TARGET TERMINATION RESPONSE
When PI7C8150B initiates a delayed read transaction, the abnormal target responses can be
passed back to the initiator. Other target responses depend on how much data the initiator
requests. Table 3-9 shows the response to each type of target termination that occurs
during a delayed read transaction.
PI7C8150B repeats a delayed read transaction until one of the following conditions is met:
PI7C8150B makes 2
After PI7C8150B makes 2
target bus, PI7C8150B asserts P_SERR_L if the primary SERR_L enable bit is set (bit 8 of
Target Termination
Target Disconnect
Target Abort
Target Termination
Normal
Target Retry
Target Disconnect
Target Abort
PI7C8150B completes at least one data transfer.
PI7C8150B receives a master abort.
PI7C8150B receives a target abort.
24
(default) read attempts resulting in a response of target retry.
Repsonse
Initiate write transaction for delivering remaining posted write data.
Set received-target-abort bit in the target interface status register. Assert
P_SERR# if enabled, and set the signaled-system-error bit in primary status
register.
Response
If prefetchable, target disconnect only if initiator requests more data than read
from target. If non-prefetchable, target disconnect on first data phase.
Re-initiate read transaction to target
If initiator requests more data than read from target, return target disconnect to
initiator.
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator interface
status register.
24
(default) attempts of the same delayed read transaction on the
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(default) write transaction attempts and fails to deliver all
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B