PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 15

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.3
CLOCK SIGNALS
Name
S_DEVSEL_L
S_STOP_L
S_LOCK_L
S_PERR_L
S_SERR_L
S_REQ_L[8:0]
S_GNT_L[8:0]
S_RESET_L
S_M66EN
S_CFN_L
Name
P_CLK
Pin #
175
173
172
171
169
2, 207
14, 13, 11, 10
22
153
23
Pin #
45
9, 8, 7, 6, 5, 4, 3,
19, 18, 17, 16, 15,
Page 15 of 109
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Pin #
A11
B11
C11
A12
D11
E4, E3, D2, C1,
C2, D3, A2,B3,
B4
G1, F1, F2, G3,
F4, E1, E2,F3,
D1
H1
D15
H2
Pin #
M4
Type
Type
I/OD
STS
STS
STS
STS
TS
O
I
I
I
I
ADVANCE INFORMATION
Description
Secondary Device Select (Active LOW): Asserted by
the target indicating that the device is accepting the
transaction. As a master, PI7C8150B waits for the
assertion of this signal within 5 cycles of S_FRAME_L
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven to a de-asserted state for one cycle.
Secondary STOP (Active LOW): Asserted by the
target indicating that the target is requesting the initiator
to stop the current transaction. Before tri-stated, it is
driven to a de-asserted state for one cycle.
Secondary LOCK (Active LOW): Asserted by the
master for multiple transactions to complete.
Secondary Parity Error (Active LOW): Asserted
when a data parity error is detected for data received on
the secondary interface. Before being tri-stated, it is
driven to a de-asserted state for one cycle.
Secondary System Error (Active LOW): Can be
driven LOW by any device to indicate a system error
condition.
Secondary Request (Active LOW): This is asserted by
an external device to indicate that it wants to start a
transaction on the secondary bus. The input is externally
pulled up through a resistor to VDD.
Secondary Grant (Active LOW): PI7C8150B asserts
this pin to access the secondary bus. PI7C8150B de-
asserts this pin for at least 2 PCI clock cycles before
asserting it again. During idle and S_GNT_L asserted,
PI7C8150B will drive S_AD, S_CBE, and S_PAR.
Secondary RESET (Active LOW): Asserted when any
of the following conditions are met:
1.
2.
When asserted, all control signals are tri-stated and
zeroes are driven on S_AD, S_CBE, and S_PAR.
Secondary Interface 66MHz Operation:
In synchronous mode, this input is used to specify if
PI7C8150B is running at 66MHz on the secondary side.
When HIGH, the Secondary bus may run at 66MHz.
When LOW, the Secondary bus may only run at
33MHz.
If P_M66EN is pulled LOW, the S_M66EN is also
driven LOW.
In asynchronous mode, S_M66EN is an input pin and
operates independently from P_M66EN. S_M66EN
should be pulled up to a logic “1” when the secondary
frequency is 66MHz, or pulled down to a logic “0” when
the secondary frequency is 33MHz.
Secondary Bus Central Function Control Pin: When
tied LOW, it enables the internal arbiter. When tied
HIGH, an external arbiter must be used. S_REQ_L[0] is
reconfigured to be the secondary bus grant input, and
S_GNT_L[0] is reconfigured to be the secondary bus
request output. S_CFN_L has a weak internal pull-
down resistor.
Description
Primary Clock Input: Provides timing for all
transactions on the primary interface.
April 2009 – Revision 1.08
Signal P_RESET_L is asserted.
Secondary reset bit in bridge control register in
configuration space is set.
PI7C8150B