PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 52

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.3
For upstream transactions, when PI7C8150B detects a read data parity error on the primary
bus, the following events occur:
PI7C8150B returns to the initiator the data and parity that was received from the target.
When the initiator detects a parity error on this read data and is enabled to report it, the
initiator asserts PERR_L two cycles after the data transfer occurs. It is assumed that the
initiator takes responsibility for handling a parity error condition; therefore, when
PI7C8150B detects PERR_L asserted while returning read data to the initiator, PI7C8150B
does not take any further action and completes the transaction normally.
DELAYED WRITE TRANSACTIONS
When PI7C8150B detects a data parity error during a delayed write transaction, the
initiator drives data and data parity, and the target checks parity and conditionally asserts
PERR_L.
For delayed write transactions, a parity error can occur at the following times:
When a delayed write transaction is normally queued, the address, command, address
parity, data, byte enable bits, and data parity are all captured and a target retry is returned to
the initiator. When PI7C8150B detects a parity error on the write data for the initial
delayed write request transaction, the following events occur:
PI7C8150B forwards the bad parity with the data back to the initiator on the primary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
primary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8150B completes the transaction normally.
PI7C8150B asserts P_PERR_L two cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
PI7C8150B sets the detected parity error bit in the primary status register.
PI7C8150B sets the data parity detected bit in the primary status register, if the
primary interface parity-error-response bit is set in the command register.
PI7C8150B forwards the bad parity with the data back to the initiator on the secondary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
secondary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
PI7C8150B completes the transaction normally.
During the original delayed write request transaction
When the initiator repeats the delayed write request transaction
When PI7C8150B completes the delayed write transaction to the target
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
April 2009 – Revision 1.08
PI7C8150B