PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 28

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.6.3
Table 3-4. Read Prefetch Address Boundaries
Table 3-5. Read Transaction Prefetching
If extra read transactions could have side effects, for example, when accessing a FIFO, use
non-prefetchable read transactions to those locations. Accordingly, if it is important to
retain the value of the byte enable bits during the data phase, use non-prefetchable read
transactions. If these locations are mapped in memory space, use the memory read
command and map the target into non-prefetchable (memory-mapped I/O) memory space
to use non-prefetching behavior.
READ PREFETCH ADDRESS BOUNDARIES
PI7C8150B imposes internal read address boundaries on read pre-fetched data. When a
read transaction reaches one of these aligned address boundaries, the PI7C8150B stops pre-
fetched data, unless the target signals a target disconnect before the read pre-fetched
boundary is reached. When PI7C8150B finishes transferring this read data to the initiator,
it returns a target disconnect with the last data transfer, unless the initiator completes the
transaction before all pre-fetched read data is delivered. Any leftover pre-fetched data is
discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB
address boundary, or until the initiator de-asserts FRAME_L. Section 3.6.6 describes flow-
through mode during read operations.
Table 3-4 shows the read pre-fetch address boundaries for read transactions during non-
flow-through mode.
- does not matter if it is prefetchable or non-prefetchable
* don’t care
See Section 4.3 for detailed information about prefetchable and non-prefetchable address spaces.
Type of Transaction
Configuration Read
I/O Read
Memory Read
Memory Read
Memory Read
Memory Read Line
Memory Read Line
Memory Read Multiple
Memory Read Multiple
Type of Transaction
I/O Read
Configuration Read
Memory Read
Memory Read Line
Memory Read Multiple
Address Space
-
-
Non-Prefetchable
Prefetchable
Prefetchable
-
-
-
-
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Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Prefetching always used
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Cache
(CLS)
*
*
*
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
Line
Size
ADVANCE INFORMATION
April 2009 – Revision 1.08
Prefetch
Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address
boundary
Cache line address boundary
16-DWORD aligned address
boundary
Cache line boundary
32-DWORD aligned address
boundary
2X of cache line boundary
Aligned
PI7C8150B
Address