PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 17

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2.5
2.2.6
GENERAL PURPOSE I/O INTERFACE SIGNALS
JTAG BOUNDARY SCAN SIGNALS
CFG66 /
SCAN_EN_H /
CLK_RATE
MS0, MS1
Name
GPIO[3:0]
Name
TCK
TMS
TDO
TDI
TRST_L
125
155, 106
Pin #
24, 25, 27, 28
Pin #
133
132
130
129
134
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
K16
B14, R16
Pin #
J3, J2, J1, K1
Pin #
H15
H14
H16
J15
G15
Type
Type
TS
O
I
I
I
I
I
I
ADVANCE INFORMATION
This is a multiplexed pin that has 3 functions (2 in
synchronous mode and 1 in asynchronous mode).
CFG66 - 66MHz Configuration (synchronous mode):
This pin is used to designate 66MHz operation. Tie
HIGH to enable 66MHz operation or tie LOW to
designate 33MHz operation.
SCAN_EN_H - Full-Scan Enable Control
(synchronous mode): When SCAN_EN_H is LOW,
full-scan is in shift operation. When SCAN_EN_H is
HIGH, full-scan is in parallel operation. Note: Valid only
in test mode. Pin is CFG66 in normal operation.
CLK_RATE – S_CLKOUT divider (asynchronous
mode): Determines the S_CLKOUT frequency relation
to ASYNC_CLK_IN.
0: S_SCLKOUT is half the frequency of
ASYNC_CLK_IN.
1: S_CLKOUT is the same frequency as
ASYNC_CLK_IN.
Mode Selection: Selector for Asynchronous or
Synchronous mode.
Description
General Purpose I/O Data Pins: The 4 general-
purpose signals are programmable as either input-only
or bi-directional signals by writing the GPIO output
enable control register in the configuration space.
Description
Test Clock. Used to clock state information and data
into and out of the PI7C8150B during boundary scan.
Test Mode Select. Used to control the state of the Test
Access Port controller.
Test Data Output. Used as the serial output for the test
instructions and data from the test logic.
Test Data Input. Serial input for the JTAG instructions
and test data.
Test Reset. Active LOW signal to reset the Test Access
Port (TAP) controller into an initialized state.
April 2009 – Revision 1.08
MS0
0
0
1
1
MS1
0
1
0
1
PI7C8150B
Description
RESERVED
RESERVED
Synchronous Mode
Asynchronous Mode