PI7C8150BNDIE Pericom Semiconductor, PI7C8150BNDIE Datasheet - Page 89

• Manufacturer Part Number: PI7C8150BNDIE
• Description: IC PCI-PCI BRIDGE ASYNC 256-PBGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BNDIE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
1
2
3
4
5
6
7
Function
Posted Write
Parity Error
Posted Write
Non-Delivery
Target Abort
During Posted
Write
Master Abort On
Posted Write
Delayed Write
Non-Delivery
Delayed Read –
No Data From
Target
Reserved
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/O
Page 89 of 109
Description
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer delayed write data after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it receives a
master abort when attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Reserved. Returns 0 when read. Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
24
April 2009 – Revision 1.08
attempts.
24
attempts.
24
24
attempts.
attempts.
PI7C8150B