M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 129

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

Table 2-3.
28529-DSH-001-K
Port Offset
Address
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x30
0x31
0x0F
0x1F
0x2F
UDF2
TXHDR1
TXHDR2
TXHDR3
TXHDR4
TXIDL1
TXIDL2
TXIDL3
TXIDL4
RXHDR1
RXHDR2
RXHDR3
RXHDR4
RXMSK1
RXMSK2
RXMSK3
RXMSK4
RXIDL1
RXIDL2
RXIDL3
RXIDL4
IDLMSK1
IDLMSK2
IDLMSK3
IDLMSK4
ENCELLT
ENCELLR
TXCELLINT
RXCELLINT
TXCELL
RXCELL
IDLCNTL
IDLCNTH
Port Control and Status Registers (2 of 3)
Name
—
—
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
R
R
R
R
R
R
Mindspeed Proprietary and Confidential
Mindspeed Technologies
One-second
Latching
(1)
(1)
(2)
(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UDF2 Control Register
Transmit Cell Header Control Register 1
Transmit Cell Header Control Register 2
Transmit Cell Header Control Register 3
Transmit Cell Header Control Register 4
Transmit Idle Cell Header Control Register 1
Transmit Idle Cell Header Control Register 2
Transmit Idle Cell Header Control Register 3
Transmit Idle Cell Header Control Register 4
Receive Cell Header Control Register 1
Receive Cell Header Control Register 2
Receive Cell Header Control Register 3
Receive Cell Header Control Register 4
Receive Cell Mask Control Register 1
Receive Cell Mask Control Register 2
Receive Cell Mask Control Register 3
Receive Cell Mask Control Register 4
Receive Idle Cell Header Control Register 1
Receive Idle Cell Header Control Register 2
Receive Idle Cell Header Control Register 3
Receive Idle Cell Header Control Register 4
Receive Idle Cell Mask Control Register 1
Receive Idle Cell Mask Control Register 2
Receive Idle Cell Mask Control Register 3
Receive Idle Cell Mask Control Register 4
Transmit Cell Interrupt Control Register
Receive Cell Interrupt Control Register
Reserved, set to a logical 0
Reserved, set to a logical 0
Transmit Cell Interrupt Indication Control Register
Receive Cell Interrupt Indication Control Register
Transmit Cell Status Control Register
Receive Cell Status Control Register
Idle Cell Receive Counter (low byte)
Idle Cell Receive Counter (high byte)
Description (Continued)
®
Registers
Number
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