M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 167

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.2.3
The PMODE register controls the port-level software resets, source loopback, and physical layer interface mode.
28529-DSH-001-K
Footnote:
(1) These bits should only be changed when the device or port logic reset is asserted.
Bit
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0x04—PMODE (Port Mode Control Register)
PrtMstRst
PrtLgcRst
SrcLoop
FeLnLoop
SrcLoopMode
PhyType[2]
PhyType[1]
PhyType[0]
(1)
Name
(1)
(1)
(1)
(1)
(1)
Mindspeed Proprietary and Confidential
Mindspeed Technologies
When written to a logical 1, this bit initiates a Port Master Reset. All internal state machines
associated with this port are reset and all control registers for this port, except this one, assume
their default values. Only bits 0–6 in this register are overwritten with their default values.
When written to a logical 1, this bit initiates a Port Logic Reset. All internal state machines
associated with this port are reset but all registers (0x00–0x3F) listed as “Type: W/R” in
3
When written to a logical 1, this bit enables a source loopback. The line transmit clock and data
outputs are connected to the line receive clock and data inputs. Refer to
Source loopback mode 0, the device is automatically configured for General Purpose mode
(ignoring the contents of the PhyType[2:0] bits).
Enables Far-end line loopback. In this mode, the receive data is processed by the TC block and
looped back at the UTOPIA interface to the transmit side. Refer to
When source loopback is enabled (when SrcLoop is written to a logic 1), this bit select between
the two types of source loopback as follows:
0 - Source Loopback 0 selected
1 - Source Loopback 1 selected
These bits determine the Physical Layer Interface Mode:
good design practice would have them tied high.)
are unaltered. Output signals for this port are three-state during Port Logic Reset.
In General Purpose Mode, the SPRxSync and SPTxSync pins are ignored. (However,
000—T1 mode
001—E1 mode
010—Reserved
011—Reserved
100—Reserved
101—General Purpose
®
Description
110—DSL Mode
111—Power Down
Figure
Figure
1-13.
1-12. During
Registers
Table 2-
152