M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 165
M28529G-12
Manufacturer Part Number
M28529G-12
Description
ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
Manufacturer
Mindspeed Technologies
Datasheet
1.M28529G-12.pdf
(309 pages)
Specifications of M28529G-12
Package
484BGA
Utopia Type
Level 2
Typical Operating Supply Voltage
1.8|3.3 V
Minimum Operating Supply Voltage
1.71|3.135 V
Maximum Operating Supply Voltage
1.89|3.465 V
Maximum Output Rate
8.192 Mbps
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Table 2-10.
2.2
2.2.1
The SUMINT register indicates the one-second interrupts, external framer interrupts, and port summary interrupts.
28529-DSH-001-K
Footnote:
(1) This bit is a summary indication of any interrupt events that occurred in the indicated registers. This bit is a pointer to the next interrupt
Address
0xe00-
0xe30
0xe31
0xe32
0xdfb
0xdfd
0xe2F
0xdfa
0xdfc
0xdfe
Bit
0xdff
7
6
5
4
3
2
1
0
indication register to be read. This bit will be cleared when the interrupt bits in the corresponding interrupt indication registers are read
and automatically cleared.
IMA_RX_GRP32_STAT_CTL_CHANGE
IMA_RX_GRP32_ACTUAL_GRP_ID
IMA_RX_GRP32_STAT_CTL
IMA_RX_GRP32_TIMING_INFO
IMA_RX_GRP32_TEST_CTL
IMA_RX_GRP32_TX_TEST_PATTERN
CELL_CAP_PAYLDn
CAP_FAC
CAP_CNTL
CAP_STAT
Default
—
—
0
0
0
0
0
0
IMA Control and Status Registers (33 of 33)
TC Registers
0x00—SUMINT (Summary Interrupt Indication Status Register)
TxCellInt
RxCellInt
(1)
Name
(1)
Name
—
—
—
—
—
—
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0.
Reserved, set to a logical 0
Reserved, set to a logical 0.
When a logical 1 is read, this bit indicates a Transmit Cell Interrupt. This interrupt is a summary
interrupt and signifies that an interrupt indication occurred in the TxCellInt register (0x2C).
When a logical 1 is read, this bit indicates a Receive Cell Interrupt. This interrupt is a summary
interrupt and signifies that an interrupt indication occurred in the RxCellInt register (0x2D).
ATM Cell Capture Registers
Rx GRP 32 SCCI
Rx GRP 32 Rx Group ID
Rx GRP 32 Status / Control
Rx GRP 32 Timing Control
Rx GRP 32 Test Control
Rx GRP 32 Tx Test Pattern
Cell Capture Payload Contents Registers
Capture Facility Register
Capture Control Register
Capture Status Register
Description (Continued)
®
Description
Registers
Number
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