M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 186

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.2.38
The ENCELLR register controls which of the interrupts listed in the RxCellInt register (0x2D) appear on the
MicroInt* pin (pin AA1), provided that both EnRxCellInt (bit 0) in the ENSUMINT register (0x01) and EnPortInt bit in
the appropriate ENSUMPORTn (n= 0 - 3) register (0xF06, 0xF08, 0xF0A or 0xF0C) for this port are enabled, and
EnIntPin (bit 3) in the GENCTRL register (0xF00) is enabled.
2.2.39
The TXCELLINT register indicates that a change of status has occurred within the transmit status signals.
28529-DSH-001-K
Footnote:
(1) Single event—A 0 to 1 transition on the corresponding status bit causes this interrupt to occur, provided that this interrupt has been
Bit
Bit
enabled by the corresponding enable bit. Reading this interrupt register clears this interrupt.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Default
Default
—
—
—
—
—
—
1
1
1
1
1
1
1
1
0
0
0x29—ENCELLR (Receive Cell Interrupt Control Register)
0x2C—TXCELLINT (Transmit Cell Interrupt Indication Status Register)
EnLOCDInt
EnHECDetInt
EnHECCorrInt
EnCellRcvdInt
EnIdleRcvdInt
EnNonMatchInt
EnNonZerGFCInt
ParErrInt
SOCErrInt
TxOvflInt
RxOvflInt
CellSentInt
Name
Name
(1)
(1)
(1)
(1)
(1)
—
—
—
—
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When written to a logical 1, this bit enables a Loss of Cell Delineation Interrupt.
When written to a logical 1, this bit enables a HEC Error Detected Interrupt.
When written to a logical 1, this bit enables a HEC Error Corrected Interrupt.
Reserved, write to a logical 0.
When written to a logical 1, this bit enables a Cell Received Interrupt.
When written to a logical 1, this bit enables an Idle Cell Received Interrupt.
When written to a logical 1, this bit enables a Non-matching Cell Received Interrupt.
When written to a logical 1, this bit enables a Non-zero GFC Received Interrupt.
When a logical 1 is read, this bit indicates that a Parity Error occurred.
When a logical 1 is read, this bit indicates that a Start of Cell Error occurred.
When a logical 1 is read, this bit indicates that a Transmit FIFO Overflow occurred.
When a logical 1 is read, this bit indicates that a Receive FIFO Overflow occurred.
When a logical 1 is read, this bit indicates that a cell has been sent.
Reserved for factory test, ignore.
Reserved, set to a logical 0.
Reserved, write to a logical 0.
®
Description
Description
Registers
171