M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 259

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.7
The ATM Cell Capture registers allow an ATM cell to be captured from a facility for diagnostic purposes.
2.7.1
These registers hold the 48 byte payload contents of a captured ATM Cell. These registers are read-only.
2.7.2
The capture facility register configures the facility that the ATM cells will be captured from.
2.7.3
The capture control register enables the capture circuit to store an incoming ATM cell as well as determine the type
of ATM cell stored
28529-DSH-001-K
Bit
7-0
Bit
7-5
4-0
Bit
7-2
1
0
Default
Default
Default
—
—
0
0
0
0
NOTE:
ATM Cell Capture Registers
0xE00-0xE2F—CELL_CAP_PAYLDn (Capture Payload Contents Register)
0xE30—CAP_FAC (Capture Facility Register)
0xE31—CAP_CNTL (Capture Control Register)
ATMPLDn
CAPTYPE
CAPFCL
Name
Name
Name
ENCAP
When a facility is configured to be part of an IMA Group, a valid cell stream must be present
on the input port or the values contained in these registers are undefined. The values in
these registers are also undefined for a maximum of two seconds following the creation of
a group containing the specified facility in 0xE30. If the facility is configured for
passthrough mode, the above restrictions do not apply.
—
—
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Contains one byte of the 48 byte payload contents of a captured ATM Cell. The first byte is stored
in register 0xE00 and the remainder of the 48 bytes are stored consecutively in registers up to
location 0xE2F.
Reserved
This field is programmed with the facility that ATM cells will be captured from.
Reserved
This bit selects whether the next incoming ICP cell is stored or simply the next ATM cell,
regardless of type, is stored.
0 = ICP Cell only
1 = Any cell (Data Cell, Filler Cell, or ICP/SICP Cell)
Enables the capture circuit to store the next incoming cell qualified by the cell type programmed
in bit 1.
This bit is written to a ‘1’ to arm the capture circuit to store the ATM cell.
This bit is should be written to a ‘0’ once the ATM cell is captured. See register 0xE32 for the
capture status.
®
Description
Description
Description
Registers
244