M28529G-12 Mindspeed Technologies, M28529G-12 Datasheet - Page 209

• Manufacturer Part Number: M28529G-12
• Description: ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of M28529G-12

• Package: 484BGA
• Utopia Type: Level 2
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.71|3.135 V
• Maximum Operating Supply Voltage: 1.89|3.465 V
• Maximum Output Rate: 8.192 Mbps

2.4.13
This register controls the UTOPIA loopbacks on the PHY side of the IMA block.
2.4.14
This register provides a single bit that can be used by a diagnostic test routine to verify the connectivity of the
microprocessor address lines to the IMA device. This bit is read-only.
2.4.15
This register provides an isolated 8 bit storage register that can be used by a diagnostic test routine to verify the
connectivity of the microprocessor data lines to the IMA device.
28529-DSH-001-K
7–0
Bit
7-3
1-0
Bit
Bit
2
7
6
5
4
3
2
1
0
Default
Default
Default
0x00
—
—
—
—
—
—
—
—
—
—
—
0x80C—IMA _PHY_LOOPBACK (IMA Phy Side UTOPIA Loopback)
0x80E—IMA_DIAG_XOR_BIT (IMA Diagnostic Bit)
0x80F—IMA_DIAG (IMA Diagnostic Register)
Loopback Enable
Loopback Type(s)
Address Diagnostic Bit
Data Diagnostic Register An 8 bit register that can be written and read by the processor. The register is not used within
Name
Name
Name
—
—
—
—
—
—
—
—
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Reserved. Set to 0
0 = PHY side loopback disabled.
1 = PHY side loopback enabled per bits 1:0 of this register.
0 = IMA System Loopback 0 -- uses TxClav signal(s) from PHY (TC or external)
1 = IMA System Loopback 1 -- ignores TxClav signal(s) from PHY layer
2 = IMA Line Loopback -- ignores TxClav signal(s) from PHY layer
3 = Not Defined
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Exclusive OR of address bits from previous IMA core Read access. The number of bits in the
exclusive OR operation is 11.
the IMA Block.
®
Description
Description
Description
Registers
194