CS4525-CNZ Cirrus Logic Inc, CS4525-CNZ Datasheet - Page 23

• Manufacturer Part Number: CS4525-CNZ
• Description: IC AMP AUDIO PWR 30W QUAD 48QFN
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZ

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Package / Case: 48-QFN
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 30 W
• Thd Plus Noise: 10 %
• Operating Supply Voltage: 2.5 V to 5 V
• Supply Current: 54 mA
• Maximum Power Dissipation: 180 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Audio - Load Impedance: 4 Ohms, 6 Ohms, 8 Ohms
• Audio Load Resistance: 8 Ohms, 4 Ohms
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.375 V
• Amplifier Class: D
• No. Of Channels: 4
• Supply Voltage Range: 8V To 18V
• Load Impedance: 4ohm
• Operating Temperature Range: 0°C To +70°C
• Amplifier Case Style: QFN
• No. Of Pins: 48
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1264

DS726PP2
XTI SWITCHING SPECIFICATIONS
Notes:
SYS_CLK SWITCHING SPECIFICATIONS
AGND = DGND = PGND = 0 V; T
C
PWM_SIGX SWITCHING SPECIFICATIONS
AGND = DGND = PGND = 0 V; T
External Crystal Operating Frequency
(Note 15)
XTI Duty Cycle
External Clock Operating Frequency
(Note 15)
Rising Edge RST to start of SYS_CLK
SYS_CLK Period
SYS_CLK Duty Cycle
SYS_CLK high time
SYS_CLK low time
Rise Time of PWM_SIGx
Fall Time of PWM_SIGx
L
= 20 pF.
15. See
“Clock Frequency (ClkFreq[1:0])” on page
Parameter
Parameter
Parameter
PWM_SIGx
SYS_CLK
(output)
RST
___
A
A
= 25°C; VD = 3.3 V; Input: Logic 0 = DGND; Logic 1 = VD, SYS_CLK Output:
= 25°C; VD = 3.3 V; Load = 10 pF.
Figure 9. SYS_CLK Timing from Reset
ClkFreq[1:0] = ‘00’
ClkFreq[1:0] = ‘01’
ClkFreq[1:0] = ‘10’
ClkFreq[1:0] = ‘00’
ClkFreq[1:0] = ‘01’
ClkFreq[1:0] = ‘10’
Figure 10. PWM_SIGX Timing
t
sclko
t
r
Symbol
Symbol
Symbol
F
F
t
t
t
t
sclko
clkih
sclki
CLK
CLK
clkil
t
t
r
f
t
f
69.
18.240
24.330
26.730
18.240
24.330
26.730
37.04
16.67
16.67
Min
Min
Min
45
45
-
-
-
1024*t
18.432
24.576
27.000
18.432
24.576
27.000
Typ
Typ
Typ
2.1
1.4
50
50
-
-
-
sclki
18.617
24.822
27.270
18.617
24.822
27.270
54.25
29.84
29.84
Max
Max
Max
55
55
-
-
-
CS4525
Unit
MHz
MHz
MHz
Unit
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
%
%
23