CS4525-CNZ Cirrus Logic Inc, CS4525-CNZ Datasheet - Page 69

• Manufacturer Part Number: CS4525-CNZ
• Description: IC AMP AUDIO PWR 30W QUAD 48QFN
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZ

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Package / Case: 48-QFN
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 30 W
• Thd Plus Noise: 10 %
• Operating Supply Voltage: 2.5 V to 5 V
• Supply Current: 54 mA
• Maximum Power Dissipation: 180 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Audio - Load Impedance: 4 Ohms, 6 Ohms, 8 Ohms
• Audio Load Resistance: 8 Ohms, 4 Ohms
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.375 V
• Amplifier Class: D
• No. Of Channels: 4
• Supply Voltage Range: 8V To 18V
• Load Impedance: 4ohm
• Operating Temperature Range: 0°C To +70°C
• Amplifier Case Style: QFN
• No. Of Pins: 48
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1264

DS726PP2
9. REGISTER DESCRIPTIONS
All registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state.
9.1
9.1.1
9.1.2
9.1.3
EnSysClk
7
Clock Configuration (Address 01h)
SYS_CLK Output Enable (EnSysClk)
Default = 1
Function:
This bit controls the output driver for the SYS_CLK signal. When cleared, the output driver is disabled and
the SYS_CLK pin is high-impedance. When set, the output driver is enabled.
If the SYS_CLK output is unused, this bit should be set to ‘0’b to disable the driver.
SYS_CLK Output Divider (DivSysClk)
Default = 0
Function:
This bit determines the divider for the XTAL clock signal for generating the SYS_CLK signal.
This divider is only available if the clock source is an external crystal attached to XTI/XTO and the
SYS_CLK output is enabled.
Clock Frequency (ClkFreq[1:0])
Default = 01
Function:
These bits must be set to identify the nominal clock frequency of the crystal attached to the XTI/XTO pins
or that of the input SYS_CLK signal. See the
SYS_CLK Switching Specifications
EnSysClk Setting
DivSysClk Setting
ClkFreq[1:0] Setting
0 ..........................................Output driver disabled.
1 ..........................................Output driver enabled.
0 ..........................................F
1 ..........................................F
00 ........................................18.432 MHz
01 ........................................24.576 MHz
10 ........................................27.000 MHz
11.........................................Reserved
DivSysClk
6
ClkFreq1
Output Driver State
SYS_CLK Output Frequency
Specified Nominal Input Clock Frequency
5
SYS_CLK
SYS_CLK
= F
= F
XTAL
XTAL
ClkFreq0
table on
/2
4
page 23
XTI Switching Specifications
HP/MutePol
for complete input frequency range specifications.
3
HP/Mute
2
PhaseShift
table on
1
page 23
CS4525
FreqShift
and the
0
69