CS4525-CNZ Cirrus Logic Inc, CS4525-CNZ Datasheet - Page 64

• Manufacturer Part Number: CS4525-CNZ
• Description: IC AMP AUDIO PWR 30W QUAD 48QFN
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r
• Type: Class Dr

Specifications of CS4525-CNZ

• Output Type: 2-Channel (Stereo) or 4-Channel (Quad)
• Package / Case: 48-QFN
• Max Output Power X Channels @ Load: 30W x 1 @ 4 Ohm; 15W x 2 @ 8 Ohm
• Voltage - Supply: 8 V ~ 18 V
• Features: ADC, Depop, I²C, I²S, Mute, PWM, Short-Circuit and Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Product: Class-D
• Output Power: 30 W
• Thd Plus Noise: 10 %
• Operating Supply Voltage: 2.5 V to 5 V
• Supply Current: 54 mA
• Maximum Power Dissipation: 180 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Audio - Load Impedance: 4 Ohms, 6 Ohms, 8 Ohms
• Audio Load Resistance: 8 Ohms, 4 Ohms
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 2.375 V
• Amplifier Class: D
• No. Of Channels: 4
• Supply Voltage Range: 8V To 18V
• Load Impedance: 4ohm
• Operating Temperature Range: 0°C To +70°C
• Amplifier Case Style: QFN
• No. Of Pins: 48
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1586 - REFERENCE BOARD FOR CS4525 PWM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1264

64
6.8
I²C Control Port Description and Timing
The control port is used to access the registers allowing the CS4525 to be configured for the desired oper-
ational modes and formats. The operation of the control port may be completely asynchronous with respect
to the audio sample serial port. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required. The control port operates in I²C Mode, with the CS4525 act-
ing as a slave device.
SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. A 47 kΩ pull-up
or pull-down on the AUX_LRCK/AD0 pin will set AD0, the least significant bit of the device address. A pull-
up to VD will set AD0 to ‘1’ and a pull-down to DGND will set AD0 to ‘0’. The state of AUX_LRCK/AD0 is
sensed, and AD0 is set upon the release of RESET.
The signal timings for a read and write cycle are shown in
fined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4525 after
a Start condition consists of a 7 bit device address field and a R/W bit (high for a read, low for a write). The
upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS4525, the device ad-
dress field, which is the first byte sent to the CS4525, should match 100101 followed by the setting of AD0.
The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the memory address
pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the
register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads
or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from
the CS4525 after each input byte is read, and is input to the CS4525 from the microcontroller after each
transmitted byte.
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 100101x0 (device address and write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write. (Optional.)
Send start condition.
Send 100101x1(device address and read operation).
SCL
SDA
Figure
SDA
SCL
START
34, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
0
START
1
CHIP ADDRESS (WRITE)
1
0
0
0
1
2
CHIP ADDRESS (WRITE)
1
1
3
0
0 1 AD0 0
0
4
2
1
5
3
0
6
4
1
7
5
ACK
AD0
8
6
Figure 33. Control Port Timing, I²C Write
Figure 34. Control Port Timing, I²C Read
9
INCR
7
0
10 11
6
ACK
8
5
INCR
MAP BYTE
9
12 13 14 15
4
10 11
6
3
MAP BYTE
5
2
12
4
1
13 14 15
3
16
0
ACK
2
STOP
17 18
START
1
16 17 18
0
19
ACK
1
Figure 33
20 21 22 23 24
CHIP ADDRESS (READ)
0
7
0
19
6
DATA
1
0
24 25
1
1 AD0 1
0
and
ACK
25
26
26 27 28
Figure
27 28
7
ACK
DATA +1
6
7
DATA
34. A Start condition is de-
1
0
0
ACK
DATA +1
7
7
DATA +n
6
0
1
DATA + n
7
0
ACK
CS4525
DS726PP2
STOP
0
ACK
NO
STOP