AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet
AD9577BCPZ-R7
Specifications of AD9577BCPZ-R7
Related parts for AD9577BCPZ-R7
AD9577BCPZ-R7 Summary of contents
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Data Sheet FEATURES Fully integrated dual PLL/VCO cores 1 integer-N and 1 fractional-N PLL Continuous frequency coverage from 11.2 MHz to 200 MHz Most frequencies from 200 MHz to 637.5 MHz available PLL1 phase jitter (12 kHz to 20 MHz): ...
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AD9577 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 PLL1 Characteristics .................................................................... 3 PLL1 Clock Output Jitter............................................................. 5 PLL2 Fractional-N Mode Characteristics ................................. 6 PLL2 ...
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Data Sheet SPECIFICATIONS Typical (typ) is given for 3.6 V) and T (−40°C to +85°C) variation. AC coupling capacitors of 0.1 μF used where appropriate. A Fox Electronics S ...
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AD9577 Parameter Phase Noise (106.25 MHz CMOS Output kHz At 10 kHz At 100 kHz At 1 MHz At 10 MHz At 30 MHz Phase Noise (156.25 MHz CMOS Output kHz At 10 kHz At 100 ...
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Data Sheet PLL1 CLOCK OUTPUT JITTER Table 2. 1 Parameter LVPECL INTEGRATED RANDOM PHASE JITTER RMS Jitter (625 MHz Output) RMS Jitter (156.25 MHz Output) RMS Jitter (106.25 MHz Output) LVDS INTEGRATED RANDOM PHASE JITTER RMS Jitter (625 MHz Output) ...
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AD9577 PLL2 FRACTIONAL-N MODE CHARACTERISTICS Table 3. Bleed = 1 Parameter NOISE CHARACTERISTICS Phase Noise (155.52 MHz LVPECL Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz Phase Noise (622.08 ...
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Data Sheet PLL2 INTEGER-N MODE CHARACTERISTICS Table 4. Bleed = 0 Parameter NOISE CHARACTERISTICS Phase Noise (106.25 MHz LVPECL Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz Phase Noise ...
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AD9577 Parameter Phase Noise (156.25 MHz CMOS Output kHz @ 10 kHz @ 100 kHz @ 1 MHz @ 10 MHz @ 30 MHz Phase Noise (155.52 MHz LVPECL Output kHz @ 10 kHz @ 100 ...
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Data Sheet PLL2 CLOCK OUTPUT JITTER Table 5. Bleed = 0 for Integer-N Mode, Bleed = 1 for Fractional-N Mode 1 Parameter LVPECL INTEGRATED RANDOM PHASE JITTER RMS Jitter (622.08 MHz Output) RMS Jitter (625 MHz Output) RMS Jitter (155.52 ...
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AD9577 1 Parameter CMOS INTEGRATED RANDOM PHASE JITTER RMS Jitter (155.52 MHz Output) RMS Jitter (38.88 MHz Output) LVPECL PERIOD AND CYCLE-TO-CYCLE JITTER (100 MHz OUTPUT) Output Peak-to-Peak Period Jitter Output RMS Period Jitter Output Peak-to-Peak, Cycle-to-Cycle Jitter Output RMS ...
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Data Sheet 1 Parameter LVPECL PERIOD AND CYCLE-TO-CYCLE JITTER (100.12 MHz OUTPUT) Output Peak-to-Peak Period Jitter Output RMS Period Jitter Output Peak-to-Peak, Cycle-to-Cycle Jitter Output RMS Cycle-to-Cycle Jitter LVDS PERIOD AND CYCLE-TO-CYCLE JITTER (100.12 MHz OUTPUT) Output Peak-to-Peak Period Jitter ...
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AD9577 TIMING CHARACTERISTICS Table 7. Parameter LVPECL (see Figure 2) Output Rise Time Output Fall Time Skew LVDS (see Figure 3) Output Rise Time Output Fall Time Skew CMOS (see Figure 4) ...
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Data Sheet CLOCK OUTPUTS AC coupling capacitors of 0.1 μF used where appropriate. Table 8. Parameter LVPECL CLOCK OUTPUTS Output Frequency Output Voltage Swing Duty Cycle Output High Voltage Output Low Voltage LVDS CLOCK ...
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AD9577 POWER Table 9. Parameter Min POWER SUPPLY 3.0 LVPECL POWER DISSIPATION LVDS POWER DISSIPATION CMOS POWER DISSIPATION POWER CHANGES Power-Down 1 LVPECL Channel 160 Power-Down 1 LVDS Channel 105 Power-Down 1 CMOS Channel 130 Typ Max Unit Test Conditions/Comments ...
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Data Sheet CRYSTAL OSCILLATOR Table 10. Parameter CRYSTAL SPECIFICATION Frequency ESR Load Capacitance Phase Noise Stability REFERENCE INPUT Table 11. Parameter CLOCK INPUT (REFCLK) Input Frequency Input High Voltage Input Low Voltage Input Current Input Capacitance CONTROL PINS Table 12. ...
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AD9577 ABSOLUTE MAXIMUM RATINGS Table 13. Parameter V to GND S REFCLK to GND LDO to GND XT1, XT2 to GND SSCG, MAX_BW, MARGIN, SCL, SDA, REFSEL to GND REFOUT, OUTxP, OUTxN to GND 1 Junction Temperature Storage Temperature Lead ...
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Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND). IT ...
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AD9577 Pin No. Mnemonic Description 30 VSOB1A Output Port OUT1 Power Supply. 31 SDA Serial Data Line for I 32 VSOB0A Output Port OUT0 Power Supply. 33 OUT0N LVPECL/LVDS/CMOS Clock Output. 34 OUT0P LVPECL/LVDS/CMOS Clock Output. 37 SCL Serial Clock ...
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Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS REFOUT AND PLL1 PHASE NOISE PERFORMANCE –100 –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 6. Phase Noise, REFOUT Output, 25 MHz (f –100 –110 –120 –130 –140 –150 –160 ...
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AD9577 PLL2 PHASE NOISE PERFORMANCE –110 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 12. Phase Noise, PLL2, OUT2 LVPECL, 100 MHz, Integer-N Mode ( MHz 100 ...
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Data Sheet OUTPUT JITTER 480 475 470 465 460 455 450 445 440 435 430 Figure 18. Typical Integrated Random Phase Jitter in fs rms ...
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AD9577 TYPICAL OUTPUT SIGNAL 5ns/DIV Figure 20 Typical LVPECL Differential Output Trace, 156.25 MHz 5ns/DIV Figure 21. Typical LVDS Differential Output Trace, 156.25 MHz 1ns/DIV Figure 22. Typical CMOS Output Trace, 200MHz Figure 23. Typical LVPECL Differential Output Trace, 625 ...
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Data Sheet 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 2.7 0.5pF LOAD 2.6 5.2pF LOAD 10.5pF LOAD 2 100 120 FREQUENCY (MHz) Figure 26. CMOS Single-Ended, Peak-to-Peak Output Swing vs. Frequency, for Loads of ...
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AD9577 TYPICAL SPREAD SPECTRUM PERFORMANCE CHARACTERISTICS 100.1 100.0 99.9 99.8 99.7 99.6 99.5 99.4 TIME (10µs/DIV) Figure 29. Typical Spread Spectrum Frequency Modulation Profile OUT2 96, FRAC = 0, MOD = 1000, CkDiv = 7, NumSteps = 59, ...
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Data Sheet TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain ...
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AD9577 Therefore, to accurately estimate the TJ p-p, separate measurements of the rms value of the random jitter (RJ rms) and the peak-to-peak value of the deterministic jitter (DJ p-p) must be taken. To measure the RJ rms of the ...
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Data Sheet DETAILED BLOCK DIAGRAM 22pF XT1 22pF XT2 REFCLK SCL CONTROL SDA MARGIN SSCG MAX_BW FRAC_TRIWAVE REFSEL AD9577 XTAL OSC DIVIDE VCO DIVIDERS LDO1 PLL1 VCO DIVIDE BY 2.15GHz ...
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AD9577 EXAMPLE APPLICATION 25MHz XTAL MAX_BW Achievable application frequencies include (but are not limited to) those listed in Table 16. Table 16. Typical Application Frequencies Applications Frequency (MHz) Ethernet 25, 62.5, 100, 125, 250 10G Ethernet 155.52, 156.25, 187.5, 161.1328125, ...
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Data Sheet FUNCTIONAL DESCRIPTION On the AD9577, parameters can be programmed over an I bus to provide custom output frequencies, output formats, and feature selections. However, this programming must be repeated after every power cycle of the part. The AD9577 ...
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AD9577 OUTPUT CHANNEL DIVIDERS Between each VCO and its associated chip outputs, there are two divider stages: a VCO divider that has a divide ratio between 2 and 6 and an output divider that can be set to divide between ...
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Data Sheet Table 21.PLL2 Output Driver Format Control Bits, Register DR1[5:3] FORMAT2 (PLL2) Register DR1[5:3] OUT3P/OUT3N 000 LVPECL 001 LVDS 010 2 × CMOS 011 2 × CMOS 100 2 × CMOS 101 LVPECL 110 LVPECL 111 1 2 × ...
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AD9577 PLL1 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD determines the phase difference error between the reference divider output and the feedback divider output clock edges. The outputs of this circuit are pulse-width modulated up and down signal ...
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Data Sheet The f frequency presented to OUT3 can be set according to OUT3 FRAC + ( Nb ) MOD = × PFD × OUT3 V3 D3 The loop filters required for this PLL are integrated on chip. ...
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AD9577 Integer Boundary Spurs Another mechanism for fractional spur creation is the interactions between the RF VCO frequency and the reference frequency. When these frequencies are not integer related (the point of a fractional-N synthesizer), spur sidebands appear on the ...
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Data Sheet MARGINING By asserting the MARGIN pin, a second full frequency map can be applied to the output ports. The values for the Na, V0, D0, V1, and D1 parameters, and the Nb, FRAC, MOD, V2, D2, V3, D3 ...
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AD9577 Table 26 shows the relevant register names and programmable ranges. Table 26. Registers Used to Program SSCG Operation Parameter Register Name NumSteps BS2[7:0], BS3[7] FracStep BS1[7:0] CkDiv BS3[6:0] Because the register values need to be expressed as integers, there ...
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Data Sheet MAX_BW The normal bandwidth of PLL2 is 50 kHz. This low bandwidth is required to filter the SDM phase noise. When SSCG is activated, the bandwidth is increased to 125 kHz. There is a trade-off in setting the ...
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AD9577 INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION S SLAVE ADDR, LSB = 0 (WR) A(S) S SLAVE ADDR, LSB = 0 (WR START BIT A(S) = ACKNOWLEDGE BY SLAVE START BIT SLAVE ADDRESS SDA A6 ...
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Data Sheet Table 30. Internal Register Map Register Name R/W Addr 0x40 0x1F 0 BP0 W 0x11 0 AF0 W 0x18 0 BF3 W 0x1C 0 BF0 W 0x19 BF1 W 0x1A FRAC[3:0], SDM ...
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AD9577 DEFAULT FREQUENCY MAP AND OUTPUT FORMATS 2 The power-up operation (without I C programming) of the AD9577 is represented by a default frequency map and output formats (see Table 31). Table 31. Default Parameter Values, f Parameter Value Notes ...
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Data Sheet The AD9577 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long supporting the 7-bit addresses plus the R/ W bit. The AD9577 has 31 subaddresses to enable the ...
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AD9577 TYPICAL APPLICATION CIRCUITS VSCA VSI2C REFOUT V S VSREFOUT V S VSX REFCLK 22pF XT2 22pF XT1 REFSEL V S VSCB NOT CONNECT OTHER TRACES TO PIN 15, ...
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Data Sheet VSCA VSI2C REFOUT V S VSREFOUT V VSX S REFCLK 22pF XT2 22pF XT1 REFSEL V S VSCB NOT CONNECT OTHER TRACES TO PIN 15, PIN 16, ...
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... ORDERING GUIDE Model 1 Temperature Range AD9577BCPZ −40°C to +85°C AD9577BCPZ-RL −40°C to +85°C AD9577BCPZ-R7 −40°C to +85°C AD9577-EVALZ RoHS Compliant Part refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...