AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 40

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

AD9577
DEFAULT FREQUENCY MAP AND OUTPUT
FORMATS
The power-up operation (without I
AD9577
formats (see Table 31).
Table 31. Default Parameter Values, f
Parameter
PLL1
PLL2
SSCG
Control
Na
V0
D0
V1
D1
FORMAT1
SyncCh01
Nb
FRAC
MOD
PD_SDM
Bleed
V2
D2
V3
D3
FORMAT2
SyncCh23
FracStep
NumSteps
CkDiv
EnI2C
NewAcq
PDCH0
PDCH1
PDCH2
PDCH3
PDRefOut
PDPLL1
PDPLL2
R
is represented by a default frequency map and output
Value
80 + 20 = 100
4
4
4
5
000
0
80 + 16 = 96
0
0
1
0
4
6
4
18
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
C programming) of the
Notes
f
f
OUT0/OUT1 are LVPECL
f
f
OUT2/OUT3 are LVPECL
OUT0
OUT1
OUT2
OUT3
PFD
= 156.25 MHz,
= 125 MHz
= 100 MHz,
= 33.333 MHz
= 25 MHz
Rev. 0 | Page 40 of 44
Parameter
Margining
PLL2
I
The
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCL), carry information between any devices
connected to the bus. Each slave device is recognized by a unique
address. The slave address consists of the 7 MSBs of an 8-bit
word. The 7-bit slave address of the
of the word sets either a read or write operation (see Figure 44).
Logic 1 corresponds to a read operation, and Logic 0
corresponds to a write operation.
To control the device on the bus, do the following protocol.
First, the master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA while
SCL remains high, which indicates that an address/data stream
follows. All peripherals respond to the start condition and shift
the next eight bits (the 7-bit address and the R/ W bit). The bits
are transferred from MSB to LSB. The peripheral that recognizes
the transmitted address responds by pulling the data line low
during the ninth clock pulse, which is known as the acknowledge
bit. All other devices withdraw from the bus at this point and
maintain an idle condition. The idle condition is where the device
monitors the SDA and SCL lines waiting for the start condition
and correct transmitted address. The R/ W bit determines the
direction of the data. Logic 0 on the LSB of the first byte means
that the master writes information to the peripheral, and Logic 1
on the LSB of the first byte means that the master reads
information from the peripheral.
2
C INTERFACE OPERATION
PLL1
Na
V0
D0
V1
D1
f
f
Nb
FRAC
MOD
V2
D2
V3
D3
OUT0
OUT1
AD9577
is programmed by a 2-wire, I
Value
80 + 20 = 100
4
4
4
5
156.25 MHz
125 MHz
80 + 22 = 102
0
0
2
6
4
6
AD9577
Notes
These parameters are
applied only when the
MARGIN pin = high
f
f
f
f
OUT0
OUT1
OUT2
OUT3
= 156.25 MHz,
= 125 MHz
= 212.5 MHz,
= 106.25 MHz
2
C-compatible serial bus
is 1000000. The LSB
Data Sheet