AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 30

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

AD9577
OUTPUT CHANNEL DIVIDERS
Between each VCO and its associated chip outputs, there are
two divider stages: a VCO divider that has a divide ratio between
2 and 6 and an output divider that can be set to divide between
1 and 32. This cascade of dividers allows a minimum output
channel divide ratio of 2 and a maximum of 192. With VCO
frequencies ranging between 2.15 GHz and 2.55 GHz, the part
can be programmed to spot frequencies over a continuous
frequency range of from 11.2 MHz to 200 MHz, and it can be
programmed to spot frequencies over a continuous frequency
range of 200 MHz and 637.5 MHz, with only a few small gaps.
Table 19. Divider Ratio Setting Registers
Divider
Channel 0 VCO divider
Channel 1 VCO divider
Channel 2 VCO divider
Channel 3 VCO divider
Channel 0 output divider
Channel 1 output divider
Channel 2 output divider
Channel 3 output divider
1
Asserting the SyncCh01 or SyncCh23 bits (Register ADV2[0]
or Register BDV2[0]) allows each PLL output channel to use a
common VCO divider. This feature allows the OUT0/OUT1 and
OUT2/OUT3 output ports to have minimal skew when their
relative output channel divide ratio is an integer multiple.
Duty-cycle correction circuitry ensures that the output duty cycle
remains at 50%.
Set to 00000 for divide by 32.
VCO
VCO
Figure 35. Output Channel Divider Signal Path
DIVIDER
DIVIDER
DIVIDER
DIVIDER
V0[2:0]
V1[2:0]
V2[2:0]
V3[2:0]
VCO
VCO
VCO
VCO
I
ADV0[7:5]
ADV1[7:5]
BDV0[7:5]
BDV1[7:5]
ADV0[4:0]
ADV1[4:0]
BDV0[4:0]
BDV1[4:0]
2
C Registers
OUTPUT
DIVIDER
OUTPUT
DIVIDER
OUTPUT
DIVIDER
OUTPUT
DIVIDER
D0[4:0]
D1[4:0]
D2[4:0]
D3[4:0]
Parameter
V0
V1
V2
V3
D0
D1
D2
D3
OUT0
OUT1
OUT2
OUT3
Divide
Range
2 to 6
2 to 6
2 to 6
2 to 6
1 to 32
1 to 32
1 to 32
1 to 32
Rev. 0 | Page 30 of 44
1
1
1
1
OUTPUTS
Each output port can be individually configured as either
differential LVPECL, differential LVDS, or two single-ended
LVCMOS clock outputs. The simplified equivalent circuit of the
LVDS outputs is shown in Figure 36.
The simplified equivalent circuit of the LVPECL outputs is
shown in Figure 37.
Output channels (consisting of a VCO divider, output divider, and
an output buffer) can be individually powered down to save power.
Setting PDCH0, PDCH1, PDCH2, and PDCH3 (Register BP0[1:0]
and Register DR1[7:6]) powers down the appropriate channel.
Output buffer combinations of LVDS, LVPECL, and CMOS can be
selected by setting DR1[5:0] as is shown in Table 20 and Table 21.
Table 20. PLL1 Output Driver Format Control Bits,
Register DR1[2:0]
FORMAT1 (PLL1)
Register DR1[2:0]
000
001
010
011
100
101
110
111
1
This indicates that the CMOS outputs are in phase; otherwise, they are in
antiphase.
1
Figure 37. LVPECL Outputs Simplified Equivalent Circuit
Figure 36. LVDS Outputs Simplified Equivalent Circuit
3.5mA
3.5mA
GND
OUT1P/OUT1N
LVPECL
LVDS
2 × CMOS
2 × CMOS
2 × CMOS
LVPECL
LVPECL
2 × CMOS
3.3V
OUTxP
OUTxN
OUTxP
OUTxN
OUT0P/OUT0N
LVPECL
LVDS
LVPECL
2 × CMOS
LVDS
LVDS
2 × CMOS
2 × CMOS
Data Sheet