AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 32

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

AD9577
PLL1 PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD determines the phase difference error between the
reference divider output and the feedback divider output clock
edges. The outputs of this circuit are pulse-width modulated up
and down signal pulses. These pulses drive the charge pump
circuit. The amount of charge delivered from the charge pump to
the loop filter is determined by the instantaneous phase error. The
action of the closed loop is to drive the frequency and phase error
at the input of the PFD toward zero. Figure 42 shows a block
diagram of the PFD/CP circuitry.
PLL1 VCO
PLL1 incorporates a low phase noise LC-tank VCO. This VCO
has 32 frequency bands spanning from 2.15 GHz to 2.55 GHz.
At power-up, a VCO calibration cycle begins and the correct band
is selected based on the feedback divider setting (Na). Whenever a
new feedback divider setting is called for, the VCO calibration
process must run by writing 1 followed by 0 to the NewAcq bit,
Register X0[0].
PLL1 FEEDBACK DIVIDER
The feedback divider ratio, Na, is used to set the PLL1 VCO
frequency according to Equation 3. Note that the Na value is set
by adding the offset value of 80 to the value programmed to
Register AF0[5:0], where 80 is the minimum divider Na value.
The maximum Na value is 131. For example, to set Na to 85, the
AF0[5:0] register is set to 5.
SETTING THE OUTPUT FREQUENCY OF PLL1
For example, set the output frequency (f
156.25 MHz, the output frequency (f
and both the reference frequency (f
(f
The frequency f
Equation 4.
The frequency f
Equation 5.
PFD
) to 25 MHz.
Figure 42. PFD Circuit Showing Simplified Charge Pump
FEEDBACK
DIVIDER
REFCLK
HIGH
HIGH
OUT0
OUT1
presented to OUT0 can be set according to
presented to OUT1 can be set according to
D1 Q1
D2 Q2
CLR1
CLR2
UP
DOWN
OUT1
REF
) and the PFD frequency
) on Port 1 to 100 MHz,
OUT0
GND
3.3V
) on Port 0 to
CHARGE
PUMP
CP
Rev. 0 | Page 32 of 44
To determine if both 156.25 MHz and 100 MHz can be derived
from a common f
range, use the lowest common multiple (LCM) of 156.25 MHz
and 100 MHz to determine the lowest VCO frequency that can
be divided down to provide both of these frequencies.
Therefore, set the VCO frequency to 2.5 GHz. With f
25 MHz, from Equation 3, Na must be set to 100.
For 156.25 MHz on Port 0, set
This can be achieved by setting V0 to 4 and D0 to 4. For
100 MHz on Port 1, set
This can be achieved by setting V1 to 5 and D1 to 5. With a
reference frequency of 25 MHz, the reference divider value, R,
must be set to 1 by setting Register G0[1] to 0. Table 22
summarizes the register settings for this configuration.
Table 22. Register Settings for Example PLL1 Configuration
Parameter
Na
V0
D0
V1
D1
R
PLL2 INTEGER/FRACTIONAL-N PLL
The lower PLL in Figure 32, PLL2, is a fractional-N PLL. The
input frequency to the PLL from the reference circuit is f
The VCO frequency, f
for Nb, FRAC, and MOD according to
where Nb is programmable in the 80 to 131 range. To provide
the greatest flexibility and accuracy, both the FRAC and MOD
values can be programmed to a resolution of 12 bits, where
FRAC < MOD. The VCO output frequency can tune over the
2.15 GHz to 2.55 GHz range to fractional multiples of the PFD
input frequency.
By setting each of the VCO divider (V2 and V3) and output
divider (D2 and D3) values, the VCO frequency can be divided
down to the required output frequency, independently, for each
of the output ports, OUT2 and OUT3. The f
presented to OUT2 can be set according to
LCM(156.25 MHz, 100 MHz) = 2.5 GHz
V0 × D0 = 16
V1 × D1 = 25
f
f
VCO
OUT2
2
=
=
f
f
PFD
Divide Value
100
4
4
5
5
1
PFD
VCO1
×
×
(
(
Nb
Nb
frequency in the 2.15 GHz to 2.55 GHz
VCO2
V2
+
+
, is programmed by setting the values
×
FRAC
FRAC
MOD
MOD
D2
I
AF0[5:0]
ADV0[7:5]
ADV0[4:0]
ADV1[7:5]
ADV1[4:0]
G0[1]
2
C Register
)
)
OUT2
Data Sheet
frequency
Register Value
010100
100
00100
101
00101
1
PFD
=
PFD
.
(10)
(6)
(7)
(8)
(9)