AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 41

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

Data Sheet
The
on the SDA pin is eight bits long supporting the 7-bit addresses
plus the R/ W bit. The
the user-accessible internal registers (see
interprets the first byte as the device address and the second byte as
the starting subaddress. Auto-increment mode is supported, which
allows data to be read from or written to the starting subaddress
and each subsequent address without manually addressing the
subsequent subaddress. A data transfer is always terminated by
a stop condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all registers.
Stop and start conditions can be detected at any stage of the data
transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCL high period, one start
condition, one stop condition, or a single stop condition followed
by a single start condition should be issued. If an invalid subaddress
is issued, the
to the idle condition. If the highest subaddress is exceeded while
reading back in auto-increment mode, the highest subaddress
register contents continue to be output until the master device
issues a no acknowledge, which indicates the end of a read. In a no
acknowledge condition, the SDA line is not pulled low on the ninth
pulse. See Figure 45 and Figure 46 for sample read and write data
transfers, and see Figure 47 for a more detailed timing diagram.
Table 32. I
Write/Read
W
W
W
W
W
W
W
W
W
W
W
W
W
W
AD9577
2
C Programming Example Register Writes
AD9577
acts as a standard slave device on the bus. The data
Register Name
C0
AF0
ADV0
ADV1
BF3
BF0
BF1
BF2
ABF0
BP0
BDV0
BDV1
X0
X0
does not issue an acknowledge and returns
AD9577
has 31 subaddresses to enable
Table 30
). Therefore, it
Data (Hex)
02
0A
A6
CC
15
14
D2
71
C0
04
44
B0
01
00
Rev. 0 | Page 41 of 44
Operation
Enable I
Na = 80 + 10 = 90; f
Channel 0 divides by 5 × 6 = 30; f
Channel 1 divides by 6 × 12 = 72; f
Nb = 80 + 21 = 101; F
FRAC = 333
FRAC = 333, MOD = 625
MOD = 625
Power-up SDM, release SDM reset
Turn on Bleed
Channel 2 divides by 2 × 4 = 8; f
Channel 3 divides by 5 × 16 = 80; f
Force new acquisition by toggling NewAcq
To overwrite any of the default register values, complete the
following steps:
1.
2.
3.
An example set of I
registers and program the output frequencies of both PLLs. f
is 25 MHz. A leading W represents a write command.
2
C registers
Enable the overwriting of registers by setting EnI2C,
Register C0[1].
Only write to registers that need modification from their
default value.
After all the registers have been set, a new acquisition is
initiated by toggling NewAcq, Register X0[0] from low to high
to low.
VCO1
VCO2
= 2.25 GHz
2
C commands follows. These enable the I
= 2.53832 GHz
OUT2
OUT0
OUT1
OUT3
= 317.29 MHz
= 75 MHz
= 31.25 MHz
= 31.729 MHz
AD9577
PFD
2
C