AD9577BCPZ-R7 Analog Devices Inc, AD9577BCPZ-R7 Datasheet - Page 31

• Manufacturer Part Number: AD9577BCPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of AD9577BCPZ-R7

• Lead Free Status / Rohs Status: Compliant

Data Sheet
Table 21.PLL2 Output Driver Format Control Bits,
Register DR1[5:3]
FORMAT2 (PLL2)
Register DR1[5:3]
000
001
010
011
100
101
110
111
1
LVDS uses a current mode output stage. The normal value
(default) for this current is 3.5 mA, which yields a 350 mV
output swing across a 100 Ω resistor. The LVDS outputs meet or
exceed all ANSI/TIA/EIA-644 specifications. The LVDS output
buffer should be terminated with a 100 Ω differential resistor
between the receiver input ports (see Figure 38). A recommended
termination circuit for the LVDS outputs is shown in Figure 38.
See the
A/D Converters, for more information about LVDS.
In a dc-coupled application, the LVPECL output buffer should
be terminated via a pair of 50 Ω resistors to a voltage of V
This can be implemented by using potential dividers of 127 Ω
and 83 Ω between the supplies, as shown in Figure 39.
An alternative LVPECL termination scheme for dc-coupled
applications is shown Figure 40.
This indicates that the CMOS outputs are in phase; otherwise, they are in
antiphase.
1
AN-586 Application
3.3V
LVPECL
Figure 40. LVPECL DC-Coupled Y-Termination
LVPECL
Figure 39. LVPECL DC-Coupled Termination
LVDS
Figure 38. LVDS Output Termination
V
SINGLE-ENDED
(NOT COUPLED)
T
= V
DD
2 × CMOS
2 × CMOS
OUT3P/OUT3N
LVPECL
LVDS
2 × CMOS
LVPECL
LVPECL
2 × CMOS
50Ω
50Ω
50Ω
50Ω
50Ω
50Ω
– 2V
50Ω
Note, LVDS Outputs for High Speed
100Ω
127Ω
83Ω
50Ω
50Ω
3.3V
LVPECL
LVDS
127Ω
83Ω
OUT2P/OUT2N
LVPECL
LVDS
LVPECL
2 × CMOS
LVDS
LVDS
2 × CMOS
2 × CMOS
3.3V
LVPECL
CC
− 2 V.
Rev. 0 | Page 31 of 44
In ac-coupled applications, the LVPECL output stage needs a
pair of 200 Ω pull-down resistors to GND to provide a dc path for
the output stage emitter followers (see Figure 41). The receiver must
provide an additional 50 Ω single-ended input termination.
REFERENCE OUTPUT BUFFER
A CMOS buffered copy of the reference input circuit signal is
available at the REFOUT pin. This buffer can be optionally
powered down by setting Register DR2[0], PDRefOut to Logic 0.
PLL1 INTEGER-N PLL
The upper PLL in Figure 32, PLL1, is an integer-N PLL with a
loop bandwidth of 140 kHz. The input frequency to the PLL
from the reference circuit is f
programmed by setting the value for Na, according to
where Na is programmable in the 80 to 131 range. The VCO
output frequency can tune over the 2.15 GHz to 2.55 GHz range to
integer multiples of the PFD input frequency only.
By setting each of the VCO divider (V0 and V1) and output
divider (D0 and D1) values, the VCO frequency can be divided
down to the required output frequency, independently, for each
of the output ports, OUT0 and OUT1. The f
presented to OUT0 can be set according to
The frequency f
The loop filters required for this PLL are integrated on chip.
f
VCO1
f
f
OUT
OUT
LVPECL
= f
1
0
=
=
200Ω
PFD
f
f
Figure 41. LVPECL AC-Coupled Termination
PFD
PFD
× Na
OUT1
×
×
V
V0
presented to OUT1 can be set according to
200Ω
1
0.1µF
0.1µF
Na
Na
×
×
D
D0
1
PFD
50Ω
50Ω
. The VCO frequency, f
50Ω
V
TERM
50Ω
OUT0
LVPECL
frequency
AD9577
VCO1
, is
(3)
(4)
(5)