SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 335

• Manufacturer Part Number: SAM3X8C
• Manufacturer: Atmel Corporation

22.5.2.3
22.5.3
22.6
22.7
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
System I/O Configuration
Write Protect Registers
Fixed Priority Arbitration
Round-Robin arbitration with fixed default master
if they want to access the same slave. This technique can be used for masters that mainly per-
form single accesses.
This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one
latency cycle for the fixed default master per slave. At the end of the current access, the slave
remains connected to its fixed default master. Every request attempted by this fixed default mas-
ter will not cause any latency whereas other non privileged masters will still get one latency
cycle. This technique can be used for masters that mainly perform single accesses.
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixed priority defined by the user. If two or more master’s requests
are active at the same time, the master with the highest priority number is serviced first. If two or
more master’s requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (MATRIX_PRAS and MATRIX_PRBS).
The System I/O Configuration register (CCFG_SYSIO) allows to configure I/O lines in System
I/O mode (such as ERASE) or as general purpose I/O lines. Enabling or disabling the corre-
sponding I/O lines in peripheral mode, or in PIO mode (PIO_PER or PIO_PDR registers) in the
PIO controller, has no effect. However, the direction (input or output), pull-up and other mode
control, is still managed by the PIO controller.
To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX
address space from address offset 0x000 to 0x1FC can be write-protected by setting the WPEN
bit in the MATRIX Write Protect Mode Register (MATRIX_WPMR).
If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC
is detected, then the WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR)
is set and the WPVSRC field indicates in which register the write access has been attempted.
The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR)
with the appropriate access key, WPKEY.
The protected registers are:
“Bus Matrix Master Configuration Registers”
“Bus Matrix Slave Configuration Registers”
“Bus Matrix Priority Registers For Slaves”
“Bus Matrix Master Remap Control Register”
“System I/O Configuration Register”
SAM3X/A
SAM3X/A
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