SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 366

• Manufacturer Part Number: SAM3X8C
• Manufacturer: Atmel Corporation

23.4.6.1
23.5
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DMAC Software Requirements
SAM3X/A
SAM3X/A
Abnormal Transfer Termination
When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the
DMAC_CHSRx.SUSPx bit is high, the DMAC_CHSRx.EMPTx is asserted once the contents of
the FIFO does not permit a single word of DMAC_CTRLAx.DST_WIDTH to be formed. How-
ever, there may still be data in the channel FIFO but not enough to form a single transfer of
DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remain-
ing data in the channel FIFO are not transferred to the destination peripheral. It is permitted to
remove the channel from the suspension state by writing a ‘1’ to the DMAC_CHER.RESx field
register. The DMAC transfer completes in the normal manner. n defines the channel number.
Note:
A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit,
DMAC_CHDR.ENAx, where x is the channel number. This does not mean that the channel is
disabled immediately after the DMAC_CHSR.ENAx bit is cleared over the APB interface. Con-
sider this as a request to disable the channel. The DMAC_CHSR.ENAx must be polled and then
it must be confirmed that the channel is disabled by reading back 0.
The software may terminate all channels abruptly by clearing the global enable bit in the DMAC
Configuration Register (DMAC_EN.ENABLE bit). Again, this does not mean that all channels
are disabled immediately after the DMAC_EN.ENABLE is cleared over the APB slave interface.
Consider this as a request to disable all channels. The DMAC_CHSR.ENABLE must be polled
and then it must be confirmed that all channels are disabled by reading back ‘0’.
Note:
Note:
1. If the software wishes to disable a channel n prior to the DMAC transfer completion,
2. The software can now poll the DMAC_CHSR.EMPTx bit until it indicates that the
3. The DMAC_CHER.ENAx bit can then be cleared by software once the channel n FIFO
• There must not be any write operation to Channel registers in an active channel after the
• When the destination peripheral has been defined as the flow controller, source single
• When the source peripheral has been defined as the flow controller, destination single
channel enable is made HIGH. If any channel parameters must be reprogrammed, this can
only be done after disabling the DMAC channel.
transfer requests are not serviced until the destination peripheral has asserted its Last
Transfer Flag.
transfer requests are not serviced until the source peripheral has asserted its Last Transfer
Flag.
then it can set the DMAC_CHER.SUSPx bit to tell the DMAC to halt all transfers from
the source peripheral. Therefore, the channel FIFO receives no new data.
channel n FIFO is empty, where n is the channel number.
is empty, where n is the channel number.
If a channel is disabled by software, an active single or chunk transaction is not guaranteed to
receive an acknowledgement.
If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to
the destination peripheral and is not present when the channel is re-enabled. For read sensitive
source peripherals, such as a source FIFO, this data is therefore lost. When the source is not a
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to
empty may be acceptable as the data is available from the source peripheral upon request and is
not lost.
If a channel is disabled by software, an active single or chunk transaction is not guaranteed to
receive an acknowledgement.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12