SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 815

• Manufacturer Part Number: SAM3X8C
• Manufacturer: Atmel Corporation

35.7.8.7
Figure 35-41. Header Reception
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
te RSTSTA=1
Baud Rate
US_LINIR
in US_CR
LINBK
LINID
Clock
RXD
Header Reception (Slave Node Configuration)
All the LIN Frames start with a header which is sent by the master node and consists of a Synch
Break Field, Synch Field and Identifier Field.
In Slave node configuration, the frame handling starts with the reception of the header.
The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At
any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break
Field. As long as a Break Field has not been detected, the USART stays idle and the received
data are not taken in account.
When a Break Field has been detected, the flag LINBK in the Channel Status register
(US_CSR) is set to 1 and the USART expects the Synch Field character to be 0x55. This field is
used to update the actual baud rate in order to stay synchronized (see
received Synch character is not 0x55, an Inconsistent Synch Field error is generated (see
tion
After receiving the Synch Field, the USART expects to receive the Identifier Field.
When the Identifier Field has been received, the flag LINID in the Channel Status register
(US_CSR) is set to 1. At this moment the field IDCHR in the LIN Identifier register (US_LINIR) is
updated with the received character. The Identifier parity bits can be automatically computed
and checked (see
The flags LINID and LINBK are reset by writing the bit RSTSTA to 1 in the Control register
(US_CR).
13 dominant bits (at 0)
35.7.8.14).
Break Field
Section
1 recessive bit
Delimiter
Break
(at 1)
35.7.8.9).
Start
Bit
1
0
Synch Byte = 0x55
1
0
1
0
1
0
Stop
Bit
Start
Bit
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Section
SAM3X/A
SAM3X/A
35.7.8.8). If the
Stop
Bit
Sec-
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