XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 15

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

The bottom-left portion of the figure shows the initial situa-
tion in the FPGA’s receivers at the other end of the four
channels. Due to variations in transmission delay—espe-
cially if the channels are routed through repeaters—the
FPGA fabric may not correctly assemble the bytes into com-
plete words. The bottom-left illustration shows the incorrect
assembly of data words PQPP, QRQQ, RSRR, etc.
To support correction of this misalignment, the data stream
will include special byte sequences that define correspond-
ing points in the several channels. In the bottom half of
Figure
characters. Each receiver recognizes the "P" channel bond-
ing character, and remembers its location in the buffer. At
some point, one transceiver designated as the master
instructs all the transceivers to align to the channel bonding
character "P" (or to some location relative to the channel
bonding character). After this operation, the words transmit-
ted to the FPGA fabric will be properly aligned: RRRR,
SSSS, TTTT, etc., as shown in the bottom-right portion of
Figure
aligned following the channel bonding operation, the master
transceiver must also control the clock correction operations
described in the previous section for all channel-bonded
transceivers.
Transmitter Buffer
The transmitter's buffer write pointer (TXUSRCLK) is fre-
quency-locked to its read pointer (REFCLK). Therefore,
clock correction and channel bonding are not required. The
purpose of the transmitter's buffer is to accommodate a
phase difference between TXUSRCLK and REFCLK. A
simple FIFO suffices for this purpose. A FIFO depth of four
will permit reliable operation with simple detection of over-
flow or underflow, which could occur if the clocks are not fre-
quency-locked.
CRC
The Rocket I/O transceiver CRC logic supports the 32-bit
invariant CRC calculation used by Infiniband, FibreChannel,
and Gigabit Ethernet.
On the transmitter side, the CRC logic recognizes where the
CRC bytes should be inserted and replaces four place-
holder bytes at the tail of a data packet with the computed
CRC. For Gigabit Ethernet and FibreChannel, transmitter
CRC may adjust certain trailing bytes to generate the
required running disparity at the end of the packet.
On the receiver side, the CRC logic verifies the received
CRC value, supporting the same standards as above.
The CRC logic also supports a user mode, with a simple
data
user-defined SOP and EOP characters.
Configuration
This section outlines functions that may be selected or con-
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
4, the shaded "P" bytes represent these special
4. To ensure that the channels remain properly
packet
R
stucture
beginning
and
ending
www.xilinx.com
1-800-255-7778
with
trolled by configuration. Xilinx implementation software sup-
ports 16 transceiver primitives, as shown in
Table 2: Supported Rocket I/O Transceiver Primitives
Each of the above primitives defines default values for the
configuration attributes, allowing some number of them to
be modified by the user.
Refer to the Rocket I/O User Guide for more details.
Reset / Power Down
The receiver and transmitter have their own synchronous
reset inputs. The transmitter reset recenters the transmis-
sion FIFO, and resets all transmitter registers and the
8B/10B decoder. The receiver reset recenters the receiver
elastic buffer, and resets all receiver registers and the
8B/10B encoder. Neither reset signal has any effect on the
PLLs.
The Power Down module is controlled by the POWER-
DOWN input pin on the transceiver core. The Power down
pin on the FPGA package has no effect on the transceiver
core.
Power Sequencing
Although applying power in a random order does not dam-
age the device, it is recommended to apply power in the fol-
lowing sequence to minimize power-on current:
1. Apply FPGA fabric power supplies (V
2. Apply AVCCAUXRX.
3. Apply AVCCAUXTX, V
Virtex-II Pro™ Platform FPGAs: Functional Description
GT_CUSTOM
GT_FIBRE_CHAN_1
GT_FIBRE_CHAN_2
GT_FIBRE_CHAN_4
GT_ETHERNET_1
GT_ETHERNET_2
GT_ETHERNET_4
GT_XAUI_1
GT_XAUI_2
GT_XAUI_4
GT_INFINIBAND_1
GT_INFINIBAND_2
GT_INFINIBAND_4
GT_AURORA_1
GT_AURORA_2
GT_AURORA_4
V
CCAUX
) in any order.
Fully customizable by user
Fibre Channel, 1-byte data path
Fibre Channel, 2-byte data path
Fibre Channel, 4-byte data path
Gigabit Ethernet, 1-byte data path
Gigabit Ethernet, 2-byte data path
Gigabit Ethernet, 4-byte data path
10-gigabit Ethernet, 1-byte data path
10-gigabit Ethernet, 2-byte data path
10-gigabit Ethernet, 4-byte data path
Infiniband, 1-byte data path
Infiniband, 2-byte data path
Infiniband, 4-byte data path
Xilinx protocol, 1-byte data path
Xilinx protocol, 2-byte data path
Xilinx protocol, 4-byte data path
TTX
, and V
TRX
CCINT
in any order.
Table
and
2.
15