XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 22

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
In external (non-intrusive) debug mode, the CPU core enters
stop state (stops instruction execution) when a debug event
occurs. This mode offers a debug tool non-intrusive
read-write access to all registers in the PPC405 core. Once
the CPU core is in stop state, the debug tool can start the
CPU core, step an instruction, freeze the timers, or set hard-
ware or software break points. In addition to CPU core con-
trol, the debug logic is capable of writing instructions into the
instruction cache, eliminating the need for external memory
during initial board bring up. Communication to a debug tool
using external debug mode is through the JTAG port.
Debug wait mode offers the same functionality as external
debug mode with one exception. In debug wait mode, the
CPU core goes into wait state instead of stop state after a
debug event. Wait state is identical to stop state until an
interrupt occurs. In wait state, the PPC405 core can vector
to an exception handler, service an interrupt and return to
wait state. This mode is particularly useful when debugging
real time control systems.
Functional Description: FPGA
Input/Output Blocks (IOBs)
Virtex-II Pro I/O blocks (IOBs) are provided in groups of two
or four on the perimeter of each device. Each IOB can be
used as input and/or output for single-ended I/Os. Two IOBs
can be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in
IOB blocks are designed for high-performance I/Os, sup-
porting 22 single-ended standards, as well as differential
signaling with LVDS, LDT, and bus LVDS.
Supported I/O Standards
Virtex-II Pro IOB blocks feature SelectI/O inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (V
output driver supply voltage ( V
standard (see
age (V
22
CCAUX
Switch
Matrix
Figure 9: Virtex-II Pro Input/Output Tile
Table 3
= 2.5V) is required, regardless of the I/O
and
Table
PAD4
PAD3
PAD2
PAD1
IOB
IOB
IOB
IOB
CCO
4). An auxiliary supply volt-
) is dependent on the I/O
Differential Pair
Differential Pair
DS083-2_30_010202
CCINT
Figure
= 1.5V),
www.xilinx.com
1-800-255-7778
9.
Real-time trace debug mode is always enabled. The debug
logic continuously broadcasts instruction trace information
to the trace port. When a debug event occurs, the debug
logic signals an external debug tool to save instruction trace
information before and after the event. The number of
instructions traced depends on the trace tool.
Debug events signal the debug logic to stop the CPU core,
put the CPU core in debug wait state, cause a debug excep-
tion or save instruction trace information.
Big Endian and Little Endian Support
The PPC405 core supports big endian or little endian byte
ordering for instructions stored in external memory. Since
the PowerPC architecture is big endian internally, the ICU
rearranges the instructions stored as little endian into the
big endian format. Therefore, the instruction cache always
contains instructions in big endian format so that the byte
ordering is correct for the execution unit. This feature allows
the 405 core to be used in systems designed to function in a
little endian environment.
standard used. For exact supply voltage absolute maximum
ratings, see
Switching Characteristics (Module
Table 3: Supported Single-Ended I/O Standards
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
GTL
GTLP
HSTL_I
HSTL_II
HSTL_III
HSTL_IV
HSTL_I_18
HSTL_II_18
HSTL_III _18
HSTL_IV_18
Standard
I/O
Virtex-II Pro™ Platform FPGAs: DC and
Output
Note (1)
Note (1)
V
3.3
3.3
2.5
1.8
1.5
3.3
3.3
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
CCO
Note (1)
Note (1)
Input
V
N/A
DS083-2 (v1.0) January 31, 2002
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.3
3.3
3.3
Advance Product Specification
3.3
2.5
1.8
1.5
CCO
3).
Input
V
0.75
0.75
1.08
1.08
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.8
1.0
0.9
0.9
0.9
0.9
REF
Termination
Voltage
Board
(V
0.75
0.75
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.2
1.5
1.5
1.5
0.9
0.9
1.8
1.8
TT
)
R