XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 80

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Switching Characteristics
CLB Distributed RAM Switching Characteristics
Table 34: CLB Distributed RAM Switching Characteristics
CLB Shift Register Switching Characteristics
Table 35: CLB Shift Register Switching Characteristics
80
Notes:
1.
Notes:
1.
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Clock CLK
Sequential Delays
Setup and Hold Times Before/After Clock CLK
Clock CLK
Clock CLK to X/Y outputs (WE active) in 16 x 1 mode
Clock CLK to X/Y outputs (WE active) in 32 x 1 mode
Clock CLK to F5 output
BX/BY data inputs (DIN)
F/G address inputs
CE input (WE)
Minimum Pulse Width, High
Minimum Pulse Width, Low
Minimum clock period to meet address write cycle time
Clock CLK to X/Y outputs
Clock CLK to X/Y outputs
Clock CLK to XB output via MC15 LUT output
Clock CLK to YB output via MC15 LUT output
Clock CLK to Shiftout
Clock CLK to F5 output
BX/BY data inputs (DIN)
CE input (WS)
Minimum Pulse Width, High
Minimum Pulse Width, Low
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
Description
Description
www.xilinx.com
1-800-255-7778
T
SRLDS
T
T
T
T
T
WES
WSS
T
Symbol
Symbol
T
T
T
T
T
SHCKO16
SHCKO32
SHCKOF5
T
T
T
DS
AS
T
T
T
REGXB
REGYB
REGF5
T
REG32
CKSH
SRPH
SRPL
WPH
WPL
REG
WC
/T
/T
/T
/T
/T
AH
DH
WEH
SRLDH
WSH
–8
–8
Speed Grade
Speed Grade
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
–
–
7
7
–
–
6
6
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
Units
Units
R