XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 39

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Table 14: Virtex-II Pro Logic Resources Available in All CLBs
18 Kb Block SelectRAM Resources
Introduction
Virtex-II Pro devices incorporate large amounts of 18 Kb
block SelectRAM. These complement the distributed Selec-
tRAM resources that provide shallow RAM structures imple-
mented in CLBs. Each Virtex-II Pro block SelectRAM is an
18 Kb true dual-port RAM with two independently clocked
and independently controlled synchronous ports that
access a common storage area. Both ports are functionally
identical. CLK, EN, WE, and SSR polarities are defined
through configuration.
Each port has the following types of inputs: Clock and Clock
Enable, Write Enable, Set/Reset, and Address, as well as
separate Data/parity data inputs (for write) and Data/parity
data outputs (for read).
Operation is synchronous; the block SelectRAM behaves
like a register. Control, address and data inputs must (and
need only) be valid during the set-up time window prior to a
rising (or falling, a configuration option) clock edge. Data
outputs change as a result of the same clock edge.
Configuration
The Virtex-II Pro block SelectRAM supports various config-
urations, including single- and dual-port RAM and various
data/address aspect ratios. Supported memory configura-
tions for single- and dual-port modes are shown in
Table 15: Dual- and Single-Port Configurations
Single-Port Configuration
As a single-port RAM, the block SelectRAM has access to
the 18 Kb memory locations in any of the 2K x 9-bit,
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
Notes:
1. The carry-chains and SOP chains can be split or cascaded.
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP50
Device
16K x 1 bit
8K x 2 bits
4K x 4 bits
R
CLB Array:
Column
16 x 22
40 x 22
40 x 34
56 x 46
88 x 70
Row x
Number
22,592
Slices
1,408
3,008
4,928
9,280
of
512 x 36 bits
1K x 18 bits
2K x 9 bits
Number
of LUTs
18,560
45,184
2,816
6,016
9,856
Table
www.xilinx.com
1-800-255-7778
15.
Max Distributed
SelectRAM or
Shift Register
157,696
296,960
722,944
45,056
96,256
(bits)
1K x 18-bit, or 512 x 36-bit configurations and to 16 Kb
memory locations in any of the 16K x 1-bit, 8K x 2-bit, or
4K x 4-bit configurations. The advantage of the 9-bit, 18-bit
and 36-bit widths is the ability to store a parity bit for each
eight bits. Parity bits must be generated or checked exter-
nally in user logic. In such cases, the width is viewed as
8 + 1, 16 + 2, or 32 + 4. These extra parity bits are stored
and behave exactly as the other bits, including the timing
parameters. Video applications can use the 9-bit ratio of
Virtex-II Pro block SelectRAM memory to advantage.
Each block SelectRAM cell is a fully synchronous memory
as illustrated in
bus widths are identical.
Dual-Port Configuration
As a dual-port RAM, each port of block SelectRAM has
access to a common 18 Kb memory resource. These are
fully synchronous ports with independent control signals for
each port. The data widths of the two ports can be config-
ured independently, providing built-in bus-width conversion.
Table 16
ports A and B.
Virtex-II Pro™ Platform FPGAs: Functional Description
Figure 35: 18 Kb Block SelectRAM Memory in
illustrates the different configurations available on
Number of
Flip-Flops
18,560
45,184
Figure
2,816
6,016
9,856
DI
DIP
ADDR
WE
EN
SSR
CLK
18-Kbit Block SelectRAM
Single-Port Mode
35. Input data bus and output data
Carry Chains
Number of
140
44
44
68
92
DOP
DO
DS031_10_102000
(1)
Chains
Number
of SOP
112
176
32
80
80
(1)
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