XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 65

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XC2VP20-6FF1152C

Manufacturer Part Number
XC2VP20-6FF1152C
Description
Pro Platform FPGA
Manufacturer
Xilinx, Inc.
Datasheet

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Table 19: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics (Continued)
Rocket I/O Switching Characteristics
Table 20: Rocket I/O Reference Clock Switching Characteristics
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
Notes:
1.
Clock
REFCLK frequency range
REFCLK frequency tolerance
REFCLK rise time
REFCLK fall time
REFCLK duty cycle
REFCLK total jitter
Clock recovery frequency acquisition time
Clock recovery phase acquisition time
Bit error rate
BRAMISOCMCLK minimum pulse
width, high
BRAMISOCMCLK minimum pulse
width, low
REFCLK frequency is typically 1/20 of serial data rate.
R
Description
Description
REFCLK
80%
20%
(1)
Figure 1: Reference Clock (REFCLK) Timing Parameters
T
FCLK
Symbol
T
T
F
T
F
T
T
T
DCREF
PHASE
BER
GCLK
GTOL
LOCK
RCLK
FCLK
GJTT
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
1-800-255-7778
Symbol
T
T
T
IPWH
IPWL
RCLK
peak-to-peak
Conditions
20% – 80%
20% – 80%
-8
Speed Grade
Min
40
45
DS083-3_01_101801
All Speed Grades
-7
Note(1)
Typ
960
50
10
-6
156.25
10
±100
Max
55
40
–12
ns, min
ns, min
Units
Units
MHz
ppm
bits
ns
ns
ps
µs
%
65

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