XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 85

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted
Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
Table 42: Global Clock Set-Up and Hold for LVCMOS25 Standard, With DCM
DS083-3 (v1.0) January 31, 2002
Advance Product Specification
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to
Global Clock Input Signal for
LVCMOS25 Standard.
For data input with different standards,
adjust the setup time delay by the values
shown in
Characteristics Standard
Adjustments, page
No Delay
Global Clock and IFF with DCM
IFF = Input Flip-Flop or Latch
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
DCM output jitter is already included in the timing calculation.
IOB Input Switching
R
Description
71.
T
PSDCM
Symbol
/T
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
PHDCM
1-800-255-7778
XC2VP20
XC2VP50
XC2VP2
XC2VP4
XC2VP7
Device
–8
Speed Grade
–
7
–
6
Units
ns
ns
ns
ns
ns
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