XC2VP20-6FF1152C Xilinx, Inc., XC2VP20-6FF1152C Datasheet - Page 43

• Manufacturer Part Number: XC2VP20-6FF1152C
• Description: Pro Platform FPGA
• Manufacturer: Xilinx, Inc.

Locations / Organization
Multiplier organization is identical to the 18 Kb SelectRAM
organization, because each multiplier is associated with an
18 Kb block SelectRAM resource.
Table 20: Multiplier Resources
In addition to the built-in multiplier blocks, the CLB elements
have dedicated logic to implement efficient multipliers in
logic. (Refer to
page
Global Clock Multiplexer Buffers
Virtex-II Pro devices have 16 clock input pins that can also
be used as regular user I/Os. Eight clock pads center on
both the top edge and the bottom edge of the device, as
illustrated in
The global clock multiplexer buffer represents the input to
dedicated low-skew clock tree distribution in Virtex-II Pro
devices. Like the clock pads, eight global clock multiplexer
buffers are on the top edge of the device and eight are on
the bottom edge.
DS083-2 (v1.0) January 31, 2002
Advance Product Specification
XC2VP2
XC2VP4
XC2VP7
XC2VP20
XC2VP50
30).
Device
Figure 43: Virtex-II Pro Clock Pads
R
Figure
Virtex-II Pro
Configurable Logic Blocks (CLBs),
Device
43.
8 clock pads
8 clock pads
Columns
12
4
4
6
8
Total Multipliers
DS083-2_42_061401
216
12
28
44
88
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1-800-255-7778
Each global clock multiplexer buffer can be driven either by
the clock pad to distribute a clock directly to the device, or
by the Digital Clock Manager (DCM), discussed in
Clock Manager (DCM), page
plexer buffer can also be driven by local interconnects. The
DCM has clock output(s) that can be connected to global
clock multiplexer buffer inputs, as shown in
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II Pro device. Designers should consider the clock
distribution detail of the device prior to pin-locking and floor-
planning. (See the Virtex-II Pro User Guide.)
Virtex-II Pro™ Platform FPGAs: Functional Description
Figure 44: Virtex-II Pro Clock Multiplexer Buffer
Clock
Pad
Clock Distribution
Clock Multiplexer
Configuration
CLKOUT
CLKIN
DCM
Clock
Buffer
Clock
Pad
O
I
45. Each global clock multi-
Interconnect
DS083-2_43_122001
Figure
Local
44.
Digital
43