saa7803 NXP Semiconductors, saa7803 Datasheet - Page 15

• Manufacturer Part Number: saa7803
• Description: Saa7803 One Chip Cd Audio Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13695
Objective data sheet
6.6.2 Block diagram
Refer to
front-end in order to create a proper RF (HF) signal. This analog signal is converted to
digital by the ADC. This signal is then resampled from the ADC clock to the system clock
domain via the int/dump block.
Offset and gain on the RF signal are regulated via the AGC/AOC loop (via the analog
front-end). Remaining offset which is not removed by the analog front-end can be
removed via the digital HPF. The RF signal is then sliced by the bit detector. Clock
recovery is done by a full-digital PLL with noise filter, equalizer and sample rate convertor.
A defect detector makes it possible to hold AGC, AOC, HPF, slicer and PLL during black /
white dots. At this point in the data path, RF-samples are converted into a bitstream. The
RL2 pushback will avoid RL3s in the RF being accidently translated into RL1 or RL2 in the
bitstream.
The channel bit stream is demodulated to bytes by the EFM demodulator. Q-channel
subcode and CD-TEXT information is extracted via the Q-subcode and CD-TEXT
decoder, available for readout through the subcpu interface. The main data stream is
error-corrected by the ERCO, while the memproc takes care of the CIRC de-interleaving
and buffering of data in a FIFO. At the back-end of the channel decoder, corrupted
audio-samples can be interpolated and held, while a burst of errors can trigger the mute
block. Detection of digital silence can be used to kill the internal / external audio DAC.
Pre-emphasis on the audio-disc can be removed via the de-emphasis filter, and the data
can be 4
I
RF bit rate, with additional phase regulation on FIFO filling, or can be fully controlled via
software. CLV support is guaranteed in this way, CAV support must be regulated and
steered via software in open loop (no tacho available).
Debug information is available via registers, via the dedicated serial lines MEAS and
CFLG and via a parallel debug bus (not available when used in an application).
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S-bus and/or the EBU outputs. Motor control can be frequency regulated on incoming
Decoding, de-interleaving and Reed-Solomon error correction according to CD CIRC
standards
On-chip de-interleaving SRAM memory
Audio processing back-end with interpolate / hold, mute, kill and silence detect logic;
and de-emphasis and 4
Two data-output interfaces: I
One serial subcode output interface
Motor control for CLV or open loop or software controlled regulation with 1 or 2 motor
pins (no onboard tacho)
8-bit register map; with AHB slave interface
An interrupt output with associated interrupt, status and interrupt enable registers for
full interrupt driven operation
Debug information available via pin MEAS, pin CFLG and parallel debug-bus.
Figure
upsampled before sending to the audio DAC. CD-data is outputted via the
9. The incoming diode signals are first added and processed in the analog
Rev. 01 — 19 April 2005
upsample filter
2
S-bus and EBU
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
One chip CD audio device
SAA7803
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