saa7803 NXP Semiconductors, saa7803 Datasheet - Page 58

• Manufacturer Part Number: saa7803
• Description: Saa7803 One Chip Cd Audio Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13695
Objective data sheet
6.9.2 Static Memory Interface Unit (SMIU)
6.9.3 ROM Interface
The 3 stage pipelines can be defined in the following stages:
The microprocessors have traditionally the same width for the instructions and data. The
32-bit architecture can be more efficient in performance and could also address a much
larger address space compared to 16-bit architectures. The code density for 16-bit
architecture would be much higher than 32-bit and the performance would be greater than
half the 32-bit performance.
The ARM Thumb instructions concept addresses the issues when 16-bit instructions are
used but the performance required is for 32-bit architecture. Therefore the aim of Thumb
instruction set can be summarized as follows:
The AHB SRAM controller implements an AHB slave interface to an external SRAM. This
interface is only available in the development version of this device. The specification of
this interface is:
The ROM interface provides an interface between the onboard 4 kB SROM memory and
the ARM via the AHB bus. The specification of this interface is:
The low latency architecture is optimized for low speed operation. No wait states are used
and the ROM control signals are taken directly from the AHB bus. This means that the
maximum frequency is likely to be limited by the speed at which the control signals arrive
from the AHB master
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Fetch cycle; this is used to fetch the instruction from the memory
Decode cycle; this is used to decode the registers, used in the instructions fetched
Execute cycle; this is used to fetch the data from register banks, the shift and ALU
operations are performed and the data is written back into the memory.
Higher performance for 16-bit architecture if 16-bit instructions are to be used.
The code density achieved for 16-bit instructions in a 32-bit architecture is a much
more efficient usage of memory space.
32-bit AHB interface width
67 MHz maximum AHB operating frequency
Configured for low latency
1 kB memory word depth
32-bit data.
32-bit AHB interface width
67 MHz Maximum AHB operating frequency
Configured for low latency
8 kB memory word depth
32-bit data.
Rev. 01 — 19 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
One chip CD audio device
SAA7803
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